DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD3739
5000 PIXELS CCD LINEAR IMAGE SENSOR
The
µ
PD3739 is a CCD (Charge Coupled Device) linear image sensor which changes optical images to electrical
signal.
The
µ
PD3739 is a 2-output type CCD sensor with 2 rows of high-speed charge transfer register, which transfers
the photo signal electrons of 5000 pixels separately in odd and even pixels. It is developed as the higher sensitivity
version of the previous device, the
µ
PD35H71A. It is suitable for 400 dpi/A3 high-speed digital copiers, OCRs and
high-end business facsimiles.
FEATURES
• Valid photocell
• Photocell’s pitch
• High sensitivity
• Low image lag
• Resolution
• Data rate
• Output type
• Power supply
• Drive clock level
• On-chip circuit
• Pin assign
: 5000 pixels
: 7
µ
m
: 9.0 V/lx·s TYP. (Light source: Daylight color fluorescent lamp)
: 1 % MAX.
: 16 dot/mm (400 dpi) A3 (297
×
420 mm) size (shorter side)
: 40 MHz MAX. (20 MHz/1 output)
: 2 outputs out of phase (2 outputs in phase also supported)
: +12 V
: CMOS output under 5 V operation
: Automatic
φ
R level adjuster
: Functional compatible with the
µ
PD35H71A
• Peak response wavelength : 550 nm (green)
ORDERING INFORMATION
Part Number
Package
CCD linear image sensor 22-pin ceramic DIP (CERDIP) (400 mil)
µ
PD3739D
The information in this document is subject to change without notice.
Document No. S12744EJ1V0DS00 (1st edition)
Date Published September 1997 N
Printed in Japan
©
1997
µ
PD3739
COMPARISON CHART
Item
PIN CONFIGURATION
Pin 1
Pin 2
Pin 4
Pin 11
Pin 21
Pin 22
RECOMMENDED
OPERATING CONDITIONS
Capacitance of reset gate clock
pin external capacitor (pF)
Data rate MIN. (MHz)
ELECTRICAL
CHARACTERISTICS
Saturation exposure TYP. (Ix⋅s)
Photo response
non-uniformity (%)
TYP.
MAX.
µ
PD3739
GND
NC
NC
NC
NC
NC
1000
±
20 %
µ
PD35H71A
DGND
TEST
V
DD
V
SUB
AGND
DGND
Unspecified
0.5
0.17
4
10
0.3
0
4
6
400
7.2
9.0
10.8
3.5
MIN.
TYP.
MAX.
250
350
500
375
2143
0
400
600
0.7
In phase outputs operating
timing is added
Unspecified
0.29
±5
±10
1.0
–3
–1, +3
+6
Unspecified
4.15
5.2
6.25
3.0
400
500
800
500
Undefined
Unspecified
250
500
Undefined
Out of phase outputs
operation only
Minus and plus value
Minus and plus value
Undefined
Average dark signal TYP. (mV)
Dark signal
non-uniformity (mV)
MIN.
TYP.
MAX.
Power consumption MAX. (mW)
Response (V/Ix⋅s)
MIN.
TYP.
MAX.
Offset level TYP. (V)
Shift register clock pin
capacitance (pF)
Note
Dynamic range TYP.
(times)
Reset feed-through
noise (mV)
DR1
DR2
MIN.
TYP.
MAX.
Random noise TYP. (mV)
TIMING CHART
DEFINITIONS OF
CHARACTERISTICS ITEMS
Photo response non-uniformity
Dark signal non-uniformity
Random noise
Absolute value
Absolute value
Standard deviation of signal
level distribution by scan
RECOMMENDED SOLDERING CONDITIONS
Wave soldering is deleted
—
Note
Due to the changing of measurement conditions, and pin capacitance of each devices is almost the same.
(
µ
PD3739: Power supply = 12 V,
µ
PD35H71A: Power supply = 0 V)
2
BLOCK DIAGRAM
GND
V
OD
19
18
17
14
13
φ
R2
φ
1L2
φ
22
φ
12
1
V
OUT
2
CCD analog shift register
Transfer gate
20
S1
D9
D32
S2
Photocell
D33
S4999
Transfer gate
CCD analog shift register
V
OUT
1
3
5
6
9
S5000
10
φ
R1
φ
2L1
φ
21
φ
11
D34
Automatic
φ
R level adjuster
......
12
φ
TG
µ
PD3739
3
µ
PD3739
PIN CONFIGURATION (Top View)
CCD linear image sensor 22-pin ceramic DIP (CERDIP) (400 mil)
Ground
1
GND
NC
22
No connection
No connection
2
NC
NC
21
No connection
Output signal 1
3
V
OUT
1
V
OUT
2
20
Output signal 2
No connection
4
NC
V
OD
19
Output drain voltage
Reset gate clock 1
5
φ
R1
φ
2L1
φ
R2
φ
1L2
18
Reset gate clock 2
Last stage shift register clock 2
6
17
Last stage shift register clock 1
No connection
7
NC
NC
16
No connection
No connection
8
NC
NC
15
No connection
Shift register clock 2
9
φ
21
φ
11
NC
φ
22
φ
12
φ
TG
14
Shift register clock 2
Shift register clock 1
10
13
Shift register clock 1
No connection
11
12
Transfer gate clock
PHOTOCELL STRUCTURE DIAGRAM
5
µ
m
2
µ
m
7
µ
m
Channel stopper
Aluminum
shield
4
µ
PD3739
ABSOLUTE MAXIMUM RATINGS (T
A
= +25 ˚C)
Parameter
Output drain voltage
Shift register clock voltage
Reset gate clock voltage
Transfer gate clock voltage
Operating ambient temperature
Storage temperature
V
OD
V
φ
1
, V
φ
2
V
φ
R1
, V
φ
R2
V
φ
TG
T
A
T
stg
Symbol
Ratings
–0.3 to +15
–0.3 to +15
–0.3 to +15
–0.3 to +15
–25 to +55
–40 to +100
Unit
V
V
V
V
˚C
˚C
Caution Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability;
exceeding the ratings could cause permanent damage. The parameters apply independently.
RECOMMENDED OPERATING CONDITIONS (T
A
= –25 to +55 ˚C)
Parameter
Output drain voltage
Shift register clock high level
Shift register clock low level
Reset gate clock high level
Reset gate clock low level
Capacitance of reset gate clock pin external capacitor
Transfer gate clock high level
Transfer gate clock low level
Data rate
Symbol
V
OD
V
φ
1H
, V
φ
2H
V
φ
1L
, V
φ
2L
V
φ
R1H
, V
φ
R2H
V
φ
R1L
, V
φ
R2L
C
EXT
φ
R
V
φ
TGH
V
φ
TGL
2f
φ
R1
, 2f
φ
R2
Note
Note
Non-polar type
Conditions
MIN.
11.4
4.5
–0.3
4.5
–0.3
800
4.5
–0.3
0.5
TYP.
12.0
5.0
0
5.0
0
1000
5.0
0
2
MAX.
12.6
5.5
+0.5
5.5
+0.5
1200
5.5
+0.5
40
Unit
V
V
V
V
V
pF
V
V
MHz
Note
Input the reset gate clocks 1 and 2 (
φ
R1,
φ
R2) to pins 5 and 18, respectively, via an input resistor and a capacitor.
Use of a capacitor is indispensable. Refer to
APPLICATION CIRCUIT EXAMPLE
for the connection method.
The reset gate clock high level and low level at the IC pins (after passing through the external capacitor) varies
according to the IC, due to the on-chip automatic
φ
R level adjuster. The recommended operating conditions
of reset gate clocks 1, 2 (
φ
R1,
φ
R2) in the table above are for signals applied to the external capacitor.
Remark
φ
1 in the above tables represents
φ
11,
φ
12 and
φ
1L2.
φ
2 represents
φ
21,
φ
22 and
φ
2L1.
5
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