DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD3734A
2660 PIXELS CCD LINEAR IMAGE SENSOR
The
µ
PD3734A is a high sensitivity CCD (Charge Coupled Device) linear image sensor which changes optical
images to electrical signal.
The
µ
PD3734A has 2660 pixels and an output amplifier which has high gain and wide output range, but low noise.
Built-in sample and hold circuit converts and outputs independent signal from CCD register in every pixel to
continuous video signal. So it is easy to interface to A/D converter or Bi-level converter.
FEATURES
• Valid photocell
• Photocell’s pitch
• High sensitivity
• Resolution
• Power supply
• Drive clock level
• High speed scan
• Built-in circuit
: 2660 pixels
: 11
µ
m
: 70 V/lx·s TYP.
: 12 dot/mm
300 dpi
: +12 V
: CMOS output under 5 V operation
: 0.54 ms/line (S/H in used)
: Sample and hold circuit
Reset feed-through level clamp circuit
Clamp pulse generation circuit
Voltage amplifier
• Low noise
• Low image lag
• Pin assign
: A quarter of the
µ
PD3734
: 1 % MAX.
: Compatible with the
µ
PD3734
A4 (210
×
297 mm) size (shorter side)
• Peak response wavelength : 550 nm (green)
US letter (8.5”
×
11”) size (shorter side)
ORDERING INFORMATION
Part Number
Package
CCD linear image sensor 22-pin plastic DIP (400 mil)
µ
PD3734ACY
The information in this document is subject to change without notice.
Document No. S11454EJ1V0DS00 (1st edition)
Date Published May 1996 P
Printed in Japan
©
1996
µ
PD3734A
COMPARISON CHART
Item
PIN CONFIGURATION
RECOMMENDED
OPERATING CONDITIONS
ELECTRICAL
CHARACTERISTICS
Average dark signal MAX. (mV)
Dark signal
non-uniformity (mV)
MIN.
TYP.
MAX.
TYP.
MAX.
TYP.
MAX.
Pin 13
Data rate MAX. (MHz)
µ
PD3734ACY
No connection
5 (S/H in used)
4 (S/H not in used)
3.0
µ
PD3734CY-1
Digital GND
3 (No conditions)
8.0
–8
±4
+8
170
220
7
14
Data rate = 3 MHz
4
6
190
250
0.3
1.0
Data rate = 4 MHz
Power consumption
(mW)
Image lag (%)
Total transfer efficiency
(test conditions)
Reset feed-through
noise (mV)
MIN.
TYP.
MAX.
–900
–200
+500
4.5
0.9 (S/H in used)
0.9 (S/H not in used)
0
1000
1800
16
No definition
Bit noise TYP. (mV
p-p
)
Random noise (mV)
TIMING CHART
t
4
MIN. (ns)
t
5
MIN. (ns)
t
8
MIN. (ns)
90
70
20
Absolute value
Refer to
DEFINITIONS OF
CHARACTERISTICS ITEMS
11. Random noise
150
150
80
Minus and plus value
No definition
DEFINITIONS OF
CHARACTERISTICS ITEMS
Dark signal non-uniformity
Random noise
2
BLOCK DIAGRAM
V
OD
3
AGND 10
14
φ
2
φ
RB 21
V
OUT
17
•
•
Optical black (OB) 18 pixels, invalid 2 pixels,
valid photocell 2660 pixels, invalid 2 pixels
9
φ
TG
•
Voltage Amplifier
S/H circuit
Reset feed-through
level clamp circuit
φ
SHB
2
15
φ
1
4
AGND
µ
PD3734A
3
µ
PD3734A
PIN CONFIGURATION (Top View)
CCD linear image sensor 22-pin plastic DIP (400 mil)
No connection
1
NC
NC
22
No connection
Sample and hold clock
2
φ
SHB
V
OD
φ
RB
NC
21
Reset gate clock
Output drain voltage
3
20
No connection
Analog GND
4
AGND
NC
19
No connection
No connection
5
NC
NC
V
OUT
18
No connection
No connection
6
NC
17
Output
No connection
7
NC
NC
16
No connection
No connection
8
NC
φ
1
φ
2
15
Shift register clock 1
Transfer gate clock
9
φ
TG
14
Shift register clock 2
Analog GND
10
AGND
NC
13
No connection
No connection
11
NC
NC
12
No connection
PHOTOCELL STRUCTURE DIAGRAM
9
µ
m
2
µ
m
11
µ
m
Channel stopper
Aluminum
electrode
4
µ
PD3734A
ABSOLUTE MAXIMUM RATINGS (T
A
= +25 ˚C)
Parameter
Output drain voltage
Shift register clock voltage
Reset gate clock voltage
Transfer gate clock voltage
Sample and hold clock voltage
Operating ambient temperature
Storage temperature
V
OD
V
φ
1
, V
φ
2
V
φ
RB
V
φ
TG
V
φ
SHB
T
A
T
stg
Symbol
Ratings
–0.3 to +15
–0.3 to +15
–0.3 to +15
–0.3 to +15
–0.3 to +15
–25 to +60
–40 to +70
Unit
V
V
V
V
V
˚C
˚C
Caution Exposure to ABSOLUTE MAXIMUM RATING for extended periods may affect device reliability;
exceeding the ratings could cause permanent damage. The parameters apply independently.
RECOMMENDED OPERATING CONDITIONS (T
A
= –25 to +60 ˚C)
Parameter
Output drain voltage
Shift register clock high level
Shift register clock low level
Reset gate clock high level
Reset gate clock low level
Transfer gate clock high level
Transfer gate clock low level
Sample and hold clock high level
Sample and hold clock low level
Data rate
Symbol
V
OD
V
φ
1H
, V
φ
2H
V
φ
1L
, V
φ
2L
V
φ
RBH
V
φ
RBL
V
φ
TGH
V
φ
TGL
V
φ
SHBH
V
φ
SHBL
f
φ
RB
S/H in used
S/H not in used
Conditions
MIN.
11.4
4.5
–0.3
4.5
–0.3
4.5
–0.3
4.5
–0.3
0.2
0.2
TYP.
12.0
5.0
0
5.0
0
5.0
0
5.0
0
1
1
MAX.
12.6
5.5
+0.5
5.5
+0.5
5.5
+0.5
5.5
+0.5
5
4
Unit
V
V
V
V
V
V
V
V
V
MHz
MHz
5
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