DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD3725A
5000-BIT
×
3 CCD COLOR LINEAR IMAGE SENSOR
The
µ
PD3725A is a high sensitivity 5000-bit
×
3 CCD (Charge Coupled Device) color linear image sensor which
changes optical images to electrical signal and has the function of color separation.
The
µ
PD3725A has 3 rows of 5000-bit photocell array and 6 rows of 2500-bit charge transferred register, so it is
suitable for high resolution color image scanners and digital color copiers.
FEATURES
• Valid photocell
• Line distance
• Color filter
• Resolution
• Data rate
• Power supply
: 5000-bit
×
3
: 112
µ
m (8 lines) R(red) bit-G(green) bit, Gbit-B(blue)bit
: Primary colors (red, green and blue), pigment filter (with light resistance 10
7
lx•Hour)
: 16 dot/mm across the shorter side of a B4-size (257
×
364 mm) sheet
: 16 MHz MAX.
: +12 V
• Photocell's pitch : 14
µ
m
• Drive clock level : CMOS output under 5 V operation
• High speed scan : 320
µ
s/line
CHANGED POINTS from the
µ
PD3725D-01
• Pins 18 and 15, 17 and 14, 11 and 8, 12 and 9 are each connected inside of the device (refer to
BLOCK
DIAGRAM).
• The specification of the total transfer efficiency (TTE) is improved from 92 % to 93.5 % (MIN.) (refer to
ELECTRICAL CHARACTERISTICS).
ORDERING INFORMATION
Part Number
Package
CCD linear image sensor 24-pin ceramic DIP (600 mil)
µ
PD3725AD
The information in this document is subject to change without notice.
Document No. S11324EJ1V0DS00 (1st edition)
Date Published March 1996 P
Printed in Japan
©
1996
µ
PD3725A
BLOCK DIAGRAM
φ
R1B
20
φ
R2B
5
φ
1A1
18
φ
2A1
17
V
OD
4
7
21
GND
GND
V
OUT
2
22
CCD analog shift register 2
Transfer gate
16
...........
φ
TG1
S4999
S5000
D128
D127
S1
S2
(B)
...........
Photocell
V
OUT
1
23
Transfer gate
CCD analog shift register 1
D133
D26
15
14
φ
1A2
φ
2A2
φ
TG2
V
OUT
4
24
CCD analog shift register 4
Transfer gate
13
...........
S4999
S5000
D128
D127
S1
S2
(G)
...........
Photocell
V
OUT
3
1
Transfer gate
CCD analog shift register 3
D133
D26
12
11
φ
2A3
φ
1A3
φ
TG3
V
OUT
6
2
CCD analog shift register 6
Transfer gate
10
...........
S4999
S5000
D128
D127
S1
S2
(R)
...........
Photocell
V
OUT
5
3
Transfer gate
CCD analog shift register 5
6
19
8
9
φ
2L
φ
1L
φ
1A4
φ
2A4
2
D133
D26
µ
PD3725A
PIN CONFIGURATIONS (Top View)
CCD linear image sensor 24-pin ceramic DIP (600 mil)
Signal output 3 (GREEN)
V
OUT
3
1
24
V
OUT
4 Signal output 4 (GREEN)
Signal output 6 (RED)
V
OUT
6
2
23
V
OUT
1 Signal output 1 (BLUE)
1
1
Signal output 5 (RED)
V
OUT
5
1
3
22
V
OUT
2 Signal output 2 (BLUE)
Output drain voltage
V
OD
4
21
GND
Ground
Reset clock 2
φ
R2B
5
20
φ
R1B Reset clock 1
Last-stage shift register clock 2
φ
2L
6
19
φ
1L
Last-stage shift register clock 1
G
R
B
Ground
GND
7
18
φ
1A1
Shift register clock 1
Shift register clock 1
φ
1A4
8
17
φ
2A1
Shift register clock 2
Shift register clock 2
φ
2A4
9
16
φ
TG1 Transfer gate clock 1
5000
5000
Shift register clock 1
φ
1A3
5000
Transfer gate clock 3
φ
TG3
10
15
φ
1A2
Shift register clock 1
11
14
φ
2A2
Shift register clock 2
Shift register clock 2
φ
2A3
12
13
φ
TG2 Transter gate clock 2
PHOTOCELL STRUCTURE DIAGRAM
12
µ
m
2
µ
m
14
µ
m
Channel stopper
Aluminium
electrode
3
µ
PD3725A
ABSOLUTE MAXIMUM RATINGS (T
A
= +25
°
C)
Parameter
Output drain voltage
Shift register clock voltage
Reset signal voltage
Transfer gate signal voltage
Operating ambient temperature
Storage temperature
V
OD
V
φ
1
, V
φ
2
V
φ
R1B
, V
φ
R2B
V
φ
TG
T
A
T
stg
Symbol
Ratings
–0.3 to +15
–0.3 to +15
–0.3 to +15
–0.3 to +15
–25 to +60
–40 to +100
Unit
V
V
V
V
°C
°C
Caution Exposure to Absolute Maximum Rating for extended periods may affect device reliability; exceeding
the ratings could cause permanent damage. The parameters apply independently.
RECOMMENDED OPERATING CONDITIONS (T
A
= +25
°
C)
Parameter
Output drain voltage
Shift register clock signal high level
Shift register clock signal low level
Reset signal high level
Reset signal low level
Transfer gate signal high level
Transfer gate signal low level
Data rate
V
OD
V
φ
1H
, V
φ
2H
V
φ
1L
, V
φ
2L
V
φ
R1BH
, V
φ
R2BH
V
φ
R1BL
, V
φ
R2BL
V
φ
TGH
V
φ
TGL
2
×
f
φ
R1B
, 2
×
f
φ
R2B
Symbol
MIN.
11.4
4.5
–0.3
4.5
–0.3
4.5
–0.3
–
TYP.
12.0
5
0
5
0
5
0
2
MAX.
12.6
5.5
+0.5
5.5
+0.5
5.5
+0.5
16
Unit
V
V
V
V
V
V
V
MHz
Remark
φ
1:
φ
1A1 to
φ
1A4,
φ
1L
φ
2:
φ
2A1 to
φ
2A4,
φ
2L
4
µ
PD3725A
ELECTRICAL CHARACTERISTICS
T
A
= +25
°C,
V
OD
= 12 V, f
øR1B
, f
φ
R2B
= 1 MHz, data rate = 2 MHz, storage time = 10 ms,
light source: 3200 K halogen lamp +C-500S (infrared cut filter, t = 1 mm), input signal clock = 5 V
p-p
Parameter
Saturation voltage
Symbol
V
sat
SER
Conditions
MIN.
1.0
TYP.
1.3
0.3
0.3
0.6
MAX.
–
Unit
V
lx•s
lx•s
lx•s
Saturation exposure
SEG
SEB
Photo response non-uniformity
Average dark signal
Dark signal non-uniformity
Power consumption
Output impedance
PRNU
ADS
DSNU
P
W
Z
O
R
R
V
OUT
= 500 mV
Light shielding
Light shielding
–5
±6
0.1
0.5
300
0.5
2.71
2.66
1.45
3.87
3.80
2.07
2
4
33
6
40
98
±15
5
+5
500
1
5.03
4.91
2.70
5
8
47
%
mV
mV
mW
kΩ
V/lx•s
V/lx•s
V/lx•s
%
V
ns
%
Response
R
G
R
B
Image lag
Offset level
Note 1
Output fall delay time
Note 2
Total transfer efficiency
Register imbalance
Red response peak
Green response peak
Blue response peak
Dynamic range
Reset feed through noise
IL
V
OS
t
d
TTE
RI
V
OUT
= 500 mV
f
φ
R1B
, f
φ
R2B
= 8 MHz, data rate = 16 MHz
V
OUT
= 500 mV
93.5
0.0
4.0
630
540
460
%
nm
nm
nm
times
DR
RFSN
V
sat
/DSNU
Light shielding
2600
300
500
mV
Notes 1.
Refer to
TIMING CHART 3, 5.
2.
Each fall delay time of
φ
1L and
φ
2L (t
11
, t
27
and t
1
, t
37
) is the TYP. value (refer to
TIMING CHART 3, 5).
5
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