DATA SHEET
DATA SHEET
CMOS DIGITAL INTEGRATED CIRCUITS
P
PD2845GR
1 V, 1.3 mA, 94MHz PLL SYNTHESIZER LSI
FOR PAGER SYSTEM
DESCRIPTION
P
PD2845GR is a PLL synthesizer LSI for pager system. This LSI is manufactured using low voltage CMOS
process and therefore realized the low power consumption PLL operated on 1 V, 1.3 mA. This LSI is packaged in 16
pin plastic SSOP suitable for high-density surface mounting. So, this product contributes to produce a long-life-
battery and physically-small pager system.
FEATURES
• Operating frequency : · Input frequency : f
in
= 10 MHz to 94 MHz
· Reference oscillating frequency : f
x’tal
= 12.8 MHz
• Low Supply voltage : · PLL block : V
DD1
= 1.00 V to 1.15 V @ f
in
= 10 MHz to 70 MHz
V
DD1
= 1.05 V to 1.15 V @ f
in
= 10 MHz to 94 MHz
· Charge pump block: V
DD2
= 3.0 V ± 300 mV
• Low power consumption
•
I
DD
= 1.3 mA TYP. @ f
in
= 70 MHz, f
x’tal
= 12.8 MHz
• Equipped with power-save function
•
Serial data can be received in power-save mode.
• Packaged in 16 pin plastic SSOP suitable for high-density surface mounting.
ORDERING INFORMATION
PART NUMBER
PACKAGE
16 pin plastic SSOP
(225 mil)
16 pin plastic SSOP
(225 mil)
SUPPLYING FORM
Embossed tape 12 mm wide. QTY 2.5 k/reel
Pin 1 is in tape pull-out direction.
Embossed tape 12 mm wide. QTY 2.5 k/reel
Pin 1 is in tape roll-in direction.
P
PD2845GR-E1
P
PD2845GR-E2
* To order evaluation samples, please contact your local NEC sales office (Order number :
P
PD2845GR).
PIN ASSIGNMENT
(Top View)
V
DD1
F
IN
GND
FR
RESET
EO
EOP
EON
XI
XO
LE
CLK
DATA
PS
NC
V
DD2
Caution Electro-static sensitive devices
Document No. P12150EJ2V0DS00 (2nd edition)
(Previous No. IC-3291)
Date Published February 1997 N
Pi di J
©
1994
P
PD2845GR
INTERNAL BLOCK DIAGRAM
XI
XO
LE
CLK
DATA
PS
NC
V
DD2
16
15
14
13
12
gate
FR
11
10
9
IN
AMP
1/2
PRESCALER
DATA
CLK
LE
5 BIT
reference divider 13 BIT
latch 13 BIT
Shift register 23 BIT
latch 18 BIT
32/33
PRESCALER gate
FV
divider 13 BIT
timer
Phase
comparator
Phase detector
error out
Pch
open
drain
Nch
open
drain
TEST CIRCUIT
1
2
3
4
5
6
7
8
V
DD1
F
IN
GND
FR
RESET
EO
EOP
EON
2
P
PD2845GR
PIN EXPLANATION
PIN No.
1
2
3
4
PIN NAME
V
DD1
F
IN
GND
FR
I/O
•
I
•
O
EXPLANATION FOR FUNCTION
Supply voltage to PLL block
Frequency Input
Ground
Test pin for monitor.
Normally used as PLL, output L should be selected by test bit and this pin should be
opened. (Refer to setting for reference counter on 11 page)
Test pin for monitor reset. (Refer to RESET on 12 page)
Normally used as PLL, this pin should be grounded.
Internal charge pump output. In the case of passive filter, this output should be used.
Input signal phase f
p
vs. reference signal f
r
f
p
> f
r
: Low output
f
p
< f
r
: High output
f
p
= f
r
: High-impedance
Outputs for external charge pump. In the case of active filter, this outputs should be used.
EOP : PCH open drain
EON : NCH open drain
EON
EOP
5
RESET
I
6
EO
O
7
8
EOP
EON
O
O
9
10
11
12
13
14
15
16
V
DD2
NC
PS
DATA
CLK
LE
XO
XI
•
•
I
I
I
I
O
I
Supply voltage to charge pump.
Non Connection.
Control bias input for power-save (Refer to Power-save on 12 page).
Data input for divided ratio.
Clock input for shift register.
Latch enable input.
X’tal oscillator connection pin.
3
P
PD2845GR
ABSOLUTE MAXIMUM RATINGS (UNLESS OTHERWISE SPECIFIED, T
A
= +25 °C)
Supply Voltage
Input Voltage
Output Voltage
Output Current
Operating Ambient Temperature
Storage Temperature
V
DD1
V
DD2
V
I1
V
I2
V
O1
V
O2
I
O
T
A
T
stg
ð0.3
to 2.0
ð0.3
to 6.0
ð0.3
to V
DD1
+0.3 (Except for DATA, CLK, LE, PS pin)
ð0.3
to 6.0 (DATA, CLK, LE, PS)
ð0.3
to V
DD1
+0.3 (XO, FR)
ð0.3
to V
DD2
+0.3 (EO, EOP, EON)
10
ð10
to +50
ð55
to +125
V
V
V
V
V
V
mA
°C
°C
RECOMMENDED OPERATING RANGE
PARAMETER
Supply Voltage
V
DD2
Operating Ambient Temperature
T
A
2.85
ð10
3.0
+25
3.15
+50
V
°C
SYMBOL
V
DD1
MIN.
1.0
TYP.
1.05
MAX.
1.1
UNIT
V
4
P
PD2845GR
ELECTRICAL CHARACTERISTICS
DC PERFORMANCE (Unless otherwise specified, V
DD1
= 1.00 V to 1.15 V, V
DD2
= 2.70 to 3.30 V, T
A
=
ð
10 to +50 °C)
PARAMETER
Supply Voltage
SYMBOL
V
DD1
V
DD2
Circuit Current
I
DD1
MIN.
1.00
2.70
TYP.
1.05
3.0
1.3
MAX.
1.15
3.30
2.2
UNIT
V
V
mA
CONDITIONS
PLL Operation
P/D Charge pump block
f
in
= 70 MHz, 0.2 V
P-P
.
fx’tal = 12.8 MHz X’tal OSC IN.
V
DD1
= 1.0 V to 1.1 V
V
DD2
= 2.85 V to 3.15 V
No Input Signal, V
DD1
= 1.1 V
EO, EOP pin. V
DD2
= 2.85 V
V
OH
= V
DD2
ð0.5
V
XO pin. V
OH
= V
DD1
ð0.5
V
FR pin. V
OH
= V
DD1
ð0.5
V
EO, EON pin. V
DD2
= 2.85 V
V
OL
= 0.5 V
XO pin. V
OL
= 0.5 V
FR pin. V
OL
= 0.5 V
F
IN
, XI pin. V
IH
= V
DD1
1.0 V
F
IN
, XI pin. V
IL
= 0 V, V
DD1
1.0 V
DATA, CLK, LE, PS pin. V
IH1
= 3.85 V
DATA, CLK, LE, PS pin.
DATA, CLK, LE, PS pin.
RESET pin.
RESET pin.
EO, EOP, EON pin.
V
DD1
= 1.0 V to 1.1 V
V
DD2
= 2.85 V to 3.15 V
Data Retain Current
High Level Output Current1
High Level Output Current2
High Level Output Current3
Low Level Output Current1
Low Level Output Current2
Low Level Output Current3
High Level Input Current1
Low Level Input Current1
*2
*1
I
DR
I
OH1
I
OH2
I
OH3
I
OL1
I
OL2
I
OL3
I
IH1
I
IL1
I
IH2
V
IH1
V
IL1
V
IH2
V
IL2
I
L
0.8
u
V
DD1
0
0.8
u
V
DD1
0
ð1.0
ð0.5
ð0.1
1.0
0.4
0.4
0.4
ð0.4
1.0
10
P
A
mA
mA
mA
mA
mA
mA
*1
*1
*2
*2
*2
P
A
P
A
1.0
4.0
0.2
u
V
DD1
V
DD1
0.2
u
V
DD1
10
ð
4
*1
*2
High Level Input Current2
P
A
V
V
V
V
High Level Input Voltage1
Low Level Input Voltage1
High Level Input Voltage2
Low Level Input Voltage2
Output Leak Current
r1.0
P
A
*1
Current from IC
*2
Current into IC
AC PERFORMANCE (Unless otherwise specified, V
DD1
= 1.00 V to 1.15 V, V
DD2
= 2.70 to 3.30 V, T
A
=
ð
10 to +50
q
C)
PARAMETER
Input frequency 1
Input frequency 2
Reference Oscillating Frequency
SYMBOL
f
in1
f
in2
f
x’tal
MIN.
10
10
12.8
TYP.
MAX.
70
94
UNIT
MHz
MHz
MHz
CONDITIONS
F
IN
pin, V
in
= 0.2 V
P-P
F
IN
pin, V
in
= 0.2 V
P-P
,
V
DD1
= 1.05 V to 1.15 V
XI, XO pin
5
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