DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD17P719
4-BIT SINGLE-CHIP MICROCONTROLLER WITH
BUILT-IN HARDWARE DEDICATED TO DIGITAL TUNING SYSTEMS
The
µ
PD17P719 is produced by replacing the built-in masked ROM of the
µ
PD17717
, µ
PD17718, and
µ
PD17719
with a one-time PROM.
The
µ
PD17P719 allows programs to be written once, so that the
µ
PD17P719 is suitable for preproduction in
µ
PD17717,
µ
PD17718, or
µ
PD17719 system development or low-volume production.
When reading this document, also refer to the publications on the
µ
PD17717,
µ
PD17718, or
µ
PD17719.
The electrical characteristics (including power supply currents) and PLL analog characteristics of
the
µ
PD17P719 differ from those of the
µ
PD17717,
µ
PD17718, and
µ
PD17719. In high-volume application
set production, carefully check those differences.
FEATURES
•
•
•
Compatible with the
µ
PD17717,
µ
PD17718, and
µ
PD17719
Built-in one-time PROM
Supply voltage
: 32K bytes (16384
×
16 bits)
: PLL operation : V
DD
= 4.5 to 5.5 V
CPU operation : V
DD
= 3.5 to 5.5 V
ORDERING INFORMATION
Part number
Package
80-pin plastic QFP (14
×
14 mm, 0.65-mm pitch)
µ
PD17P719GC-3B9
The information in this document is subject to change without notice.
Document No. U12112EJ1V0DS00 (1st edition)
Date Published February 1997 J
Printed in Japan
©
1997
µ
PD17P719
FUNCTION OVERVIEW
Item
Product
(1/2)
µ
PD17717
µ
PD17718
16384
×
16 bits
(masked ROM)
1776
×
4 bits
µ
PD17719
µ
PD17P719
16384
×
16 bits
(one-time PROM)
Program memory (ROM)
12288
×
16 bits
(masked ROM)
1120
×
4 bits
General-purpose data
memory (RAM)
Instruction execution time 1.78
µ
s (with f
X
= 4.5-MHz crystal)
General-purpose ports
• I/O ports
: 46
• Input ports : 12
• Output ports : 4
• Address stack : 15 levels
• Interrupt stack : 4 levels
• DBF stack
: 4 levels (operated by software)
• External : 6 (CE rising edge and INT0 to INT4)
• Internal : 6 (timers 0 to 3, serial interfaces 0 and 1)
5
•
•
•
channels
Basic timer (clock: 10, 20, 50, 100 Hz)
: 1 channel
8-bit timer with gate counter (clock: 1 k, 2 k, 10 k, 100 kHz) : 1 channel
8-bit timer (clock: 1 k, 2 k, 10 k, 100 kHz)
: 2 channels
: 1 channel
Stack level
Interrupt
Timers
• 8-bit timer, also used for PWM (clock: 440 Hz, 4.4 kHz)
A/D converter
D/A converter
(PWM)
8 bits
×
6 channels (Hardware or software mode can be selected.)
3 channels (8-bit or 9-bit resolution, selected by software.)
Output frequency : 4.4 kHz, 440 Hz (8-bit PWM)
2.2 kHz, 220 Hz (9-bit PWM)
2 systems (4 channels)
• Selectable for 3-wire serial I/O method, SBI method, 2-wire serial I/O method, or I
2
C bus
method
Note
.
• Selectable for 3-wire serial I/O method or UART method.
Serial interface
PLL
Frequency
division
system
Reference
frequency
Charge pump
Phase comparator
• Direct frequency division system (VCOL pin (MF mode) : 0.5 to 3 MHz)
• Pulse swallow system
(VCOL pin (HF mode) : 10 to 40 MHz)
(VCOH pin (VHF mode) : 60 to 130 MHz)
Can be set to one of 13 frequencies
(1, 1.25, 2.5, 3, 5, 6.25, 9, 10, 12.5, 18, 20, 25, or 50 kHz).
2 error output pins (EO0 and EO1)
Unlock detection is enabled by software.
• Intermediate frequency (IF) measurement
P1C0/FMIFC pin : 10 to 11 MHz in FMIF mode
0.4 to 0.5 MHz in AMIF mode
P1C1/AMIFC pin : 0.4 to 0.5 MHz in AMIF mode
• External gate width measurement
P2A1/FCG1 and P2A0/FCG0 pins
Intermediate frequency
counter
Note
When ordering a mask, please consult our sales office if the I
2
C bus method is used (or when the serial
interface is accomplished by the program not by the peripheral hardware).
2
µ
PD17P719
(2/2)
Item
BEEP output
Product
µ
PD17717
µ
PD17718
µ
PD17719
µ
PD17P719
2
Output frequency : 1 kHz, 3 kHz, 4 kHz, 6.7 kHz (BEEP0 pin)
67 Hz, 200 Hz, 3 kHz, 4 kHz (BEEP1 pin)
• Power-on reset (when the power is turned on)
• Reset using the RESET pin
• Watchdog timer reset
Can be set only once at power-on: 65,536 instructions, 131,072 instructions, or non-use
can be selected.
• Stack pointer overflow/underflow reset
Can be set only once at power-on: the interrupt stack or address stack can be selected.
• CE reset (CE pin: low
→
high)
A CE reset delay timing can be set.
• Power-failure detection function
• Clock stop mode (STOP)
• Halt mode (HALT)
Reset
Standby
Supply voltage
• PLL operation : V
DD
= 4.5 to 5.5 V
• CPU operation : V
DD
= 3.5 to 5.5 V
80-pin plastic QFP (14
×
14 mm, 0.65-mm pitch)
Package
3
µ
PD17P719
(2) PROM programming mode
V
DD
0
REG
Note
(OPEN)
GND0
(H)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
2
3
4
5
6
7
(L)
8
9
10
11
12
13
14
15
16
17
(OPEN)
18
19
20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
(L)
(L)
D0
D1
D2
D3
D4
D5
D6
D7
GND2
CLK
(L)
GND1
MD3
MD2
MD1
MD0
V
DD
1
(L)
V
PP
(L)
(L)
Note
Connect to the same potential as V
DD
.
Caution The parentheses above indicate the handling of the pins not used in PROM programming mode.
L
H
: Connect each pin to GND through a resistor (470 ohms).
: Connect each pin to V
DD
through a resistor (470 ohms).
OPEN : Leave each pin open.
(OPEN)
(L)
5
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