STK22C48
16-Kbit (2 K × 8) AutoStore™ nvSRAM
16-Kbit (2 K × 8) AutoStore nvSRAM
Features
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Functional Description
The Cypress STK22C48 is a fast static RAM with a nonvolatile
element in each memory cell. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM provides
unlimited read and write cycles, while independent nonvolatile
data resides in the highly reliable QuantumTrap cell. Data
transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power-down. On
power-up, data is restored to the SRAM (the RECALL operation)
from the nonvolatile memory. A hardware STORE is initiated with
the HSB pin.
25 ns and 45 ns access times
Hands off automatic STORE on power-down with external
68 µF capacitor
STORE to QuantumTrap™ nonvolatile elements is initiated by
software, hardware, or AutoStore™ on power-down
RECALL to SRAM initiated by software or power-up
Unlimited read, write, and RECALL cycles
1,000,000 STORE cycles to QuantumTrap
100 year data retention to QuantumTrap
Single 5 V +10% operation
Commercial and industrial temperatures
28-pin 300 mil and (330 mil) Small outline integrated circuit
(SOIC) package
Restriction of hazardous substances (RoHS) compliant
Logic Block Diagram
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V
CC
V
CAP
POWER
CONTROL
STORE/
RECALL
CONTROL
Quantum Trap
32 X 512
STORE
A
5
A
6
A
7
A
8
A
9
ROW DECODER
STATIC RAM
ARRAY
32 X 512
RECALL
pr
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s
HSB
DQ
0
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
N
COLUMN I/O
INPUT BUFFERS
DQ
1
COLUMN DEC
A
0
A
1
A
2
A
3
A
4
A
10
on
ly
.
OE
CE
WE
Cypress Semiconductor Corporation
Document Number: 001-51000 Rev. *D
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised March 7, 2011
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STK22C48
Contents
Pin Configurations ........................................................... 3
Device Operation .............................................................. 4
SRAM Read ....................................................................... 4
SRAM Write ....................................................................... 4
AutoStore Operation ........................................................ 4
AutoStore Inhibit mode .................................................... 4
Hardware STORE (HSB) Operation ................................. 5
Hardware RECALL (Power Up) ........................................ 5
Data Protection ................................................................. 5
Noise Considerations....................................................... 5
Hardware Protect.............................................................. 5
Low Average Active Power.............................................. 5
Preventing Store............................................................... 6
Best Practices................................................................... 6
Maximum Ratings ............................................................. 7
Operating Range ............................................................... 7
DC Electrical Characteristics .......................................... 7
Data Retention and Endurance ....................................... 7
Capacitance ...................................................................... 8
Thermal Resistance .......................................................... 8
AC Test Conditions .......................................................... 8
AC Switching Characteristics ......................................... 9
SRAM Read Cycle ...................................................... 9
Switching Waveforms ...................................................... 9
SRAM Write Cycle ..................................................... 10
AutoStore or Power Up RECALL .................................. 11
Switching Waveform ...................................................... 11
Hardware STORE Cycle ................................................. 12
Switching Waveform ...................................................... 12
Ordering Information ...................................................... 13
Ordering Code Definitions ......................................... 13
Package Diagrams .......................................................... 14
Document Conventions ................................................. 15
Acronyms ................................................................. 15
Units of Measure ....................................................... 15
Document History Page ................................................. 16
Sales, Solutions, and Legal Information ...................... 17
Worldwide Sales and Design Support ....................... 17
Products .................................................................... 17
PSoC Solutions ......................................................... 17
Document Number: 001-51000 Rev. *D
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STK22C48
Pin Configurations
Figure 1. Pin Diagram - 28-pin SOIC
V
CAP
NC
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ0
DQ1
DQ2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
V
CC
WE
HSB
A
8
A
9
NC
OE
A
10
CE
28-SOIC
Top View
(Not To Scale)
23
22
21
20
19
18
17
16
15
DQ6
DQ5
Table 1. Pin Definitions
Pin Name
A
0
–A
10
DQ
0
–DQ
7
WE
CE
OE
V
SS
V
CC
HSB
V
CAP
NC
W
E
G
Alt
IO Type
Input
Input
Input
Input
Input or output
Bidirectional data IO lines.
Used as input or output lines depending on operation.
Write enable input, active LOW.
When the chip is enabled and WE is LOW, data on the IO
pins is written to the specific address location.
Chip enable input, active LOW.
When LOW, selects the chip. When HIGH, deselects the chip.
Output enable, active LOW.
The active LOW OE input enables the data output buffers during
read cycles. Deasserting OE HIGH causes the IO pins to tri-state.
Ground for the device.
The device is connected to ground of the system.
Ground
Power supply
Power supply inputs to the device.
Input or output
Hardware Store Busy (HSB).
When LOW, this output indicates a Hardware Store is in progress.
When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal
pull-up resistor keeps this pin high if not connected (connection optional).
Power supply
AutoStore capacitor.
Supplies power to nvSRAM during power loss to store data from SRAM
to nonvolatile elements.
No connect
No connect.
This pin is not connected to the die.
Document Number: 001-51000 Rev. *D
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Address inputs.
Used to select one of the 2,048 bytes of the nvSRAM.
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DQ3
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DQ7
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STK22C48
Device Operation
The STK22C48 nvSRAM is made up of two functional
components paired in the same physical cell. These are an
SRAM memory cell and a nonvolatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM. Data
in the SRAM is transferred to the nonvolatile cell (the STORE
operation) or from the nonvolatile cell to SRAM (the RECALL
operation). This unique architecture enables the storage and
recall of all cells in parallel. During the STORE and RECALL
operations, SRAM Read and Write operations are inhibited. The
STK22C48 supports unlimited reads and writes similar to a
typical SRAM. In addition, it provides unlimited RECALL
operations from the nonvolatile cells and up to one million
STORE operations.
Figure 2. AutoStore Mode
SRAM Write
A Write cycle is performed whenever CE and WE are LOW and
HSB is HIGH. The address inputs must be stable prior to entering
the Write cycle and must remain stable until either CE or WE
goes HIGH at the end of the cycle. The data on the common I/O
pins DQ
0–7
are written into the memory if it has valid t
SD
, before
the end of a WE controlled Write or before the end of an CE
controlled Write. Keep OE HIGH during the entire Write cycle to
avoid data bus contention on common I/O lines. If OE is left LOW,
internal circuitry turns off the output buffers t
HZWE
after WE goes
LOW.
AutoStore Operation
During normal operation, the device draws current from V
CC
to
charge a capacitor connected to the V
CAP
pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the V
CC
pin drops below V
SWITCH
, the part
automatically disconnects the V
CAP
pin from V
CC
. A STORE
operation is initiated with power provided by the V
CAP
capacitor.
Figure 2
shows the proper connection of the storage capacitor
(V
CAP
) for automatic store operation. A charge storage capacitor
between 68 µF and 220 µF (+20%) rated at 6 V should be
Document Number: 001-51000 Rev. *D
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The STK22C48 performs a Read cycle whenever CE and OE are
LOW while WE and HSB are HIGH. The address specified on
pins A
0–10
determines the 2,048 data bytes accessed. When the
Read is initiated by an address transition, the outputs are valid
after a delay of t
AA
(Read cycle 1). If the Read is initiated by CE
or OE, the outputs are valid at t
ACE
or at t
DOE
, whichever is later
(Read cycle 2). The data outputs repeatedly respond to address
changes within the t
AA
access time without the need for
transitions on any control input pins, and remains valid until
another address change or until CE or OE is brought HIGH, or
WE or HSB is brought LOW.
In system power mode, both V
CC
and V
CAP
are connected to the
+5 V power supply without the 68
μF
capacitor. In this mode, the
AutoStore function of the STK22C48 operates on the stored
system charge as power goes down. The user must, however,
guarantee that V
CC
does not drop below 3.6 V during the 10 ms
STORE cycle.
To prevent unneeded STORE operations, automatic STOREs
and those initiated by externally driving HSB LOW are ignored,
unless at least one
WRITE
operation takes place since the most
recent STORE or RECALL cycle. An optional pull-up resistor is
shown connected to HSB. This is used to signal the system that
the AutoStore cycle is in progress.
AutoStore Inhibit mode
If an automatic STORE on power loss is not required, then V
CC
is tied to ground and +5 V is applied to V
CAP
(Figure
3 on page
5).
This is the AutoStore Inhibit mode, where the AutoStore
function is disabled. If the STK22C48 is operated in this config-
uration, references to V
CC
are changed to V
CAP
throughout this
data sheet. In this mode, STORE operations are triggered with
the HSB pin. It is not permissible to change between these three
options “on the fly”.
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SRAM Read
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STK22C48
Figure 3. AutoStore Inhibit Mode
Data Protection
The STK22C48 protects data from corruption during low voltage
conditions by inhibiting all externally initiated STORE and Write
operations. The low voltage condition is detected when V
CC
is
less than V
SWITCH
. If the STK22C48 is in a Write mode (both CE
and WE are low) at power-up after a RECALL or after a STORE,
the Write is inhibited until a negative transition on CE or WE is
detected. This protects against inadvertent writes during
power-up or brown out conditions.
Noise Considerations
The STK22C48 is a high speed memory. It must have a high
frequency bypass capacitor of approximately 0.1 µF connected
between V
CC
and V
SS,
using leads and traces that are as short
as possible. As with all high speed CMOS ICs, careful routing of
power, ground, and signals reduce circuit noise.
The STK22C48 provides the HSB pin for controlling and
acknowledging the STORE operations. The HSB pin is used to
request a hardware STORE cycle. When the HSB pin is driven
LOW, the STK22C48 conditionally initiates a STORE operation
after t
DELAY
. An actual STORE cycle only begins if a Write to the
SRAM takes place since the last STORE or RECALL cycle. The
HSB pin also acts as an open drain driver that is internally driven
LOW to indicate a busy condition, while the STORE (initiated by
any means) is in progress. Pull-up this pin with an external
10 K ohm resistor to V
CAP
if HSB is used as a driver.
SRAM Read and Write operations, that are in progress when
HSB is driven LOW by any means, are given time to complete
before the STORE operation is initiated. After HSB goes LOW,
the STK22C48 continues SRAM operations for t
DELAY
. During
t
DELAY
, multiple SRAM Read operations take place. If a Write is
in progress when HSB is pulled LOW, it allows a time, t
DELAY
to
complete. However, any SRAM Write cycles requested after
HSB goes LOW are inhibited until HSB returns HIGH.
During any STORE operation, regardless of how it is initiated,
the STK22C48 continues to drive the HSB pin LOW, releasing it
only when the STORE is complete. After completing the STORE
operation, the STK22C48 remains disabled until the HSB pin
returns HIGH.
If HSB is not used, it is left unconnected.
Hardware RECALL (Power Up)
During power-up or after any low power condition (V
CC
<
V
RESET
), an internal RECALL request is latched. When V
CC
once again exceeds the sense voltage of V
SWITCH
, a RECALL
cycle is automatically initiated and takes t
HRECALL
to complete.
Document Number: 001-51000 Rev. *D
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Hardware STORE (HSB) Operation
The STK22C48 offers hardware protection against inadvertent
STORE operation and SRAM Writes during low voltage
conditions. When V
CAP
<V
SWITCH
, all externally initiated STORE
operations and SRAM Writes are inhibited. AutoStore can be
completely disabled by tying V
CC
to ground and applying +5 V to
V
CAP
. This is the AutoStore Inhibit mode; in this mode, STOREs
are only initiated by explicit request using either the software
sequence or the HSB pin.
Low Average Active Power
CMOS technology provides the STK22C48 the benefit of
drawing significantly less current when it is cycled at times longer
than 50 ns.
Figure 4 on page 6
shows the relationship between
I
CC
and Read or Write cycle time. Worst case current
consumption is shown for both CMOS and TTL input levels
(commercial temperature range, VCC = 5.5 V, 100% duty cycle
on chip enable). Only standby current is drawn when the chip is
disabled. The overall average current drawn by the STK22C48
depends on the following items:
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The duty cycle of chip enable
The overall cycle rate for accesses
The ratio of Reads to Writes
CMOS versus TTL input levels
The operating temperature
The V
CC
level
I/O loading
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