DATA SHEET
BIPOLAR ANALOG INTEGRATED CIRCUIT
µ
PC1862
BURST LOCK CLOCK GENERATOR
The
µ
PC1862 is an LSI incorporating a PLL circuit to generate nf
SC
clocks (f
SC
: color subcarrier frequency), ideal
for the processing of digital video signals as in extended definition television (EDTV) systems.
FEATURES
• VCO is incorporated.
• Horizontal and vertical sync separation circuits are incorporated (with output pins).
• Horizontal and vertical sync output pulses (TTL level)
• ACC amplifier and killer detector circuits are incorporated.
• 1/4 and 1/8 (1/2
×
1/4) frequency dividers are incorporated.
• f
SC
phase control circuits is incorporated.
• Applicable to both NTSC and PAL systems.
• Possible to input burst gate pulse from external
ORDERING INFORMATION
Part number
Package
36-pin plastic shrink SOP (300 mil)
µ
PC1862GS
The information in this document is subject to change without notice.
Document No. S11431EJ3V0DS00 (3rd edition)
Date Published December 1997 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
1991, 1996
µ
PC1862
BLOCK DIAGRAM
SSI
CSO
36
35
34
VSSI
HDF
33
32
HDO
HKO
31
SGND
HSOF2
AFCF
BGPE
CPO
VSO
HSOF1
HSOF3
SV
CC
NHSO
FIO
N/P
30
29
28
27
26
25
24
23
22
21
20
19
H
sync
SEP
V
sync
SEP
H DET
32f
H
VCO
AFC
H count down
LPF
ACC
DET
V count down
f
2
f
4
Phase
shift
ACC
AMP
Color
Killer DET
APC
nf
SC
VCO
1
SCO
2
CV
CC1
3
TINT
4
CIN
5
ACCF
6
CKO
7
CKF
8
9
10
11
12
13
14
15
16
17
18
APCF
SCOF1
SCOF3
CV
CC3
DIVS
COUT
CGND
SCOF2
CV
CC2
VCOO
ESCI
Remark
AFC : Automatic Frequency Control
ACC : Automatic Color saturation level Control
APC : Automatic Phase Control
Selecting divide ratio by DIVS pin
DIVS
H
Open
L
1/8
EXT IN with pin 18
1/4
Divide ratio
H
L
Selecting TV transmission by N/P pin
N/P pin
PAL
NTSC
TV transmission
In PAL, only correspond 4f
SC
(DIVS = L).
2
µ
PC1862
ACCF
AFCF
APCF
BGPE
CGND
CIN
CKF
CKO
COUT
CPO
CSO
CV
CC1
-CV
CC3
DIVS
ESCI
FIO
HDF
HDO
HKO
HSOF1-HSOF3
NHSO
N/P
SCO
SCOF1-SCOF3
SGND
SSI
SV
CC
TINT
VCOO
VSO
VSSI
: Chroma ACC Filter
: Horizontal Sync AFC Filter
: Chroma APC Filter
: Burst Gate Pulse from External
: Chroma GND
: Chroma Input
: Color Killer Filter
: Color Killer Output
: Chroma Output
: Clamp Pulse Output
: Composite Sync Output
: Chroma V
CC
: Divider Setting Input
: External Subcarrier Input
: Field ID Output
: Horizontal Sync Detect Filter
: Horizontal Sync Detect Output
: Horizontal Sync Killer Output
: 32f
H
VCO Filter
: Negative Horizontal Sync Output
: NTSC/PAL Mode Select
: Subcarrier Output
: f
SC
VCO Filter
: Sync GND
: Horizontal Sync Separation Input
: Sync V
CC
: Tint Control
: VCO Output
: Vertical Sync Output
: Vertical Sync Separation Input
5
京公网安备 11010802033920号
EEWORLD
