DATA SHEET
BIPOLAR ANALOG + DIGITAL INTEGRATED CIRCUIT
µ
PB1005GS
REFERENCE FREQUENCY 16.368 MHz, 2ND IF FREQUENCY 4.092 MHz
RF/IF FREQUENCY DOWN-CONVERTER +
PLL FREQUENCY SYNTHESIZER IC FOR GPS RECEIVER
DESCRIPTION
The
µ
PB1005GS is a silicon monolithic integrated circuit for GPS receiver.
This IC is designed as double
conversion RF block integrated RF/IF down-converter + PLL frequency synthesizer on 1 chip.
The
µ
PB1005GS features shrink package, fixed prescaler and supply voltage. The 30-pin plastic SSOP package
is suitable for high density surface mounting. The fixed division internal prescaler is needless to input serial counter
data. Supply voltage is 3 V. Thus, the
µ
PB1005GS can make RF block fewer components and lower power
consumption.
This IC is manufactured using NEC’s 20 GHz f
T
NESAT
TM
III silicon bipolar process. This process uses direct
silicon nitride passivation film and gold electrodes. These materials can protect the chip surface from pollution and
prevent corrosion/migration. Thus, this IC realizes excellent performance, uniformity and reliability.
FEATURES
• Double conversion
• Integrated RF block
: f
REFin
= 16.368 MHz, f
2ndIFout
= 4.092 MHz
: RF/IF frequency down-converter + PLL frequency synthesizer
• High-density surface mountable : 30-pin plastic SSOP (9.85
×
6.1
×
2.0 mm)
• Needless to input counter data : fixed division internal prescaler
• VCO side division
• Reference division
• Supply voltage
• Low current consumption
• Gain adjustable externally
:
÷
200 (÷ 25,
÷
8 serial prescaler)
:
÷
2
: V
CC
= 2.7 to 3.3 V
: I
CC
= 45.0 mA TYP.@V
CC
= 3.0 V
: Gain control voltage pin (control voltage up vs. gain down)
APPLICATION
• Consumer use GPS receiver of reference frequency 16.368 MHz, 2nd IF frequency 4.092 MHz
ORDERING INFORMATION
Part Number
Package
30-pin plastic SSOP
(7.62 mm (300))
Supplying Form
Embossed tape 16 mm wide.
Pin 1 is in tape pull-out direction.
QTY 2.5 kpcs/reel.
µ
PB1005GS-E1
Remark
To order evaluation samples, please contact your local NEC sales office. (Part number for sample
order:
µ
PB1005GS)
Caution Electro-static sensitive devices
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. P13860EJ3V0DS00 (3rd edition)
Date Published April 2000 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
1998, 2000
µ
PB1005GS
PRODUCT LINE-UP (T
A
= +25°C, V
CC
= 3.0 V)
°
Functions
(Frequency unit: MHz)
V
CC
(V)
I
CC
(mA)
6
CG
(dB)
14
T
A
(°C)
−40
to
+85
Type
General
Purpose
Wideband
Separate
IC
Part Number
Package
6-pin
minimold
6-pin super
minimold
Status
Available
µ
PC2756T
µ
PC2756TB
µ
PC2753GR
RF down-converter with osc. Tr 2.7 to 3.3
IF down-converter with gain
control amplifier
RF/IF down-converter
+ PLL synthesizer
REF = 18.414
1stIF = 28.644/2ndIF = 1.023
RF/IF down-converter
+ PLL synthesizer
REF = 16.368
1stIF = 61.380/2ndIF = 4.092
2.7 to 3.3
6.5
60 to 79
−20
to
+85
20-pin plastic
SSOP
30-pin plastic
SSOP
Discontinued
Clock
µ
PB1003GS
Frequency
Specific
1 chip IC
2.7 to 3.3
37.5
72 to 92
µ
PB1004GS
µ
PB1005GS
2.7 to 3.3
37.5
72 to 92
−20
to
+85
−40
to
+85
Available
2.7 to 3.3
45.0
72 to 92
Remark
Typical performance. Please refer to ELECTRICAL CHARACTERISTICS in detail.
To know the associated products, please refer to their latest data sheets.
SYSTEM APPLICATION EXAMPLE
GPS receiver RF block diagram
•
f
0
= 1.023 MHz in the diagram.
60f
0
RF-MIX
out
LNA
1540f
0
1540f
0
BPF
64f
0
8f
0
1/25
1600f
0
OSC
LOOP
8f
0
AMP
1stLO-OSC1
1stLO-OSC2
LO
out
V
CC
TCXO
16.368 MHz
16f
0
1/8
PD
1/2
16f
0
16.368 MHz
Buff
to Demodulator
RF-MIX
BPF
IF-MIX
in
IF-MIX
IF-MIX
out
V
GC
40f
0
LPF
2ndlF
in
1
2ndlF
in
2
2ndlFbypass
2ndlF-Amp
4f
0
4.092 MHz
Buff
to Demodulator
•
µ
PB1005GS is in
.
1575.42 MHz
from
Antenna
example:
µ
PC2749TB
REF
Caution
This diagram schematically shows only the
µ
PB1005GS’s internal functions on the system.
This diagram does not present the actual application circuits.
Data Sheet P13860EJ3V0DS00
3
µ
PB1005GS
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage
Total Circuit Current
Power Dissipation
Symbol
V
CC
I
CC
P
D
T
A
= +25°C
T
A
= +25°C
Mounted on double-sided copper clad
50
×
50
×
1.6 mm epoxy glass PWB at T
A
= +85°C
Conditions
Ratings
3.6
128
464
−40
to +85
−55
to +150
Unit
V
mA
mW
°C
°C
Operating Ambient Temperature
Storage Temperature
T
A
T
stg
RECOMMENDED OPERATING RANGE
Parameter
Supply Voltage
Operating Ambient Temperature
RF Input Frequency
1stLO Oscillating Frequency
1stIF Input Frequency
2ndLO Input Frequency
2ndIF Input/output Frequency
Symbol
V
CC
T
A
f
RFin
f
1stLOin
f
1stIFin
f
2ndLOin
f
2ndIFin
f
2ndIFout
f
REFin
f
REFout
MIN.
2.7
−40
1616.80
TYP.
3.0
+25
1575.42
1636.80
61.380
65.472
4.092
MAX.
3.3
+85
1656.80
Unit
V
°C
MHz
MHz
MHz
MHz
MHz
Reference Input/output Frequency
16.368
MHz
4
Data Sheet P13860EJ3V0DS00
µ
PB1005GS
ELECTRICAL CHARACTERISTICS (Unless otherwise specified, T
A
= +25°C, V
CC
= 3.0 V)
°
Parameter
Total Circuit Current
Symbol
I
CC
total
Conditions
I
CC
1 + I
CC
2 + I
CC
3 + I
CC
4
MIN.
32.0
TYP.
45.0
MAX.
60.0
Unit
mA
RF Down-converter Block (f
RFin
= 1575.42 MHz, f
1stLOin
= 1636.80 MHz, P
LOin
=
−10
dBm, Z
L
= Z
S
= 50
Ω)
Circuit Current 1
RF Conversion Gain
RF-SSB Noise Figure
Maximum IF Output Power
I
CC
1
CG
RF
NF
RF
P
O(sat)RF
No Signals
P
RFin
=
−40
dBm
P
RFin
=
−40
dBm
P
RFin
=
−10
dBm
6.0
12.5
7
−5.5
10.0
15.5
10
−2.5
14.0
18.5
13
+0.5
mA
dB
dB
dBm
IF Down-converter Block (f
1stIFIn
= 61.38 MHz, f
2ndLOIn
= 65.472 MHz, Z
S
= 50
Ω,
Z
L
= 2 kΩ)
Circuit Current 2
IF Voltage Conversion Gain
IF-SSB Noise Figure
Maximum 2nd IF Output
Power
Gain Control Voltage
Gain Control Range
I
CC
2
CG
(GV)IF
NF
IF
P
O(sat)IF
No Signals
at Maximum Gain, P
1stIFin
=
−50
dBm
at Maximum Gain, P
1stIFin
=
−50
dBm
at Maximum Gain, P
1stIFin
=
−20
dBm
3.4
38
8.5
−9.5
20
5.3
41
11.5
−6.5
7.2
44
14.5
−3.5
mA
dB
dB
dBm
V
GC
D
GC
Voltage at Maximum Gain of CG
IF
P
1stIFin
=
−50
dBm
1.0
V
dB
2nd IF Amplifier (f
2ndIF
= 4.092 MHz, Z
S
= 50
Ω,
Z
L
= 2 kΩ)
Circuit Current 3
Voltage Gain
Maximum Output Power
PLL Synthesizer Block
Circuit Current 4
Phase Comparing
Frequency
Reference Input Minimum
Level
Loop Filter Output Level (H)
Loop Filter Output Level (L)
Reference Output Swing
I
CC
4
f
PD
PLL All Block Operating
PLL Loop
18.5
8.0
28.5
8.184
38.5
8.4
0.4
mA
MHz
I
CC
3
G
V
P
O(sat)
No Signals
P
2ndIFin
=
−60
dBm
P
2ndIFin
=
−30
dBm
1.55
37
−14.5
2.40
40
−11.5
3.25
43
−8.5
mA
dB
dBm
V
REFin
Z
L
= 10 kΩ//20 pF (Impedance of
measurement equipment)
200
mV
P-P
V
LP(H)
V
LP(L)
V
REFout
Z
L
= 10 kΩ//2 pF (Impedance of
measurement equipment)
2.8
1.0
V
V
V
P-P
Data Sheet P13860EJ3V0DS00
5
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