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UG12U6400M8SU-9CB

Description
DRAM
Categorystorage    storage   
File Size305KB,4 Pages
ManufacturerUnigen Corporation
Download Datasheet Parametric Compare View All

UG12U6400M8SU-9CB Overview

DRAM

UG12U6400M8SU-9CB Parametric

Parameter NameAttribute value
MakerUnigen Corporation
Objectid110450731
package instruction,
Reach Compliance Codeunknown
compound_id177513824
UG12U6400M8SU
Solutions For A Real Time World
TM
Data sheets can be downloaded at www.unigen.com
SYNCHRONOUS
DRAM MODULE
SPECIFICATIONS
1G Bytes (128M x 64 bits)
204Pin DDR3 SDRAM Unbuffered SODIMM
based on 8 pcs 128M x 8 DDR2 SDRAM 8K Refresh
FEATURES
Double-data-rate architecture; two data transfers per
clock cycle
• The high-speed data
transfer is realized by the 8 bits
prefetch pipelined
architecture
• Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK transitions
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
Data mask (DM) for write data
Posted /CAS by progrmmable additive latency for better
command and data bus efficiency
• On-Die-Termination (ODT) for better signal quality
Synchronous ODT
Dynamic ODT
Asynchronous ODT
• On-Die-Thermal Sensor (ODTS): Two trip-point method
Multi Purpose Register (MPR) for temperature read out
• ZQ calibration for DQ drive and ON-Die-Termination
Progrmmable Partial Array Self-Refresh (PASR)
/RESET pin for Power-up sequence and reset function
• Extended
Self-Refresh
External
Self-Refresh
Auto
Self-Refresh
U
N
IG
EN
• Density: 1GB
• Organization
– 128M x64 bits, Single Rank
Mountinh 8 pieces of 1G bits DDR3 SDRAM sealed in FBGA
Package:
204-pin, small-outlone memory module (SODIMM)
– Height: 30.0mm
Power supply
V
DD
= 1.5V ± 0.075V
V
DDSPD
= +3.0V to+3.6V
Fast data transfer rates: PC3-12800, PC3-10600, PC3-8500,
or PC3-6400
• Eight Internal banks for concurrent operations (components)
• Interface: SSTL_15
• Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via
the mode register set [MRS])
CAS(READ) latency (CL): 5, 6, 7, 8, 9, 10 or 11
POSTED CAS ADDITIVE latency (AL): 0, CL - 1, CL - 2
Precharge: Auto precharge option for each burst access
• Refresh: Auto-refresh, self-refresh
• TC of 0°C to 95°C
– 64ms, 8,192 cycle refresh at 0°C to 85°C
– 32ms at 85°C to 95°C
• Operating case temperature range
– TC = 0°C to 95°C
C
O
N
FI
SPEED INFORMATION
Module Marking
-8AB
-8BB
CAS Latency
CL5
CL6
CL6
CL7
CL8
CL7
CL8
CL9
CL8
CL9
CL10
CL11
SPEED
2.5ns
2.5ns
1.875ns
1.875ns
1.875ns
1.5ns
1.5ns
1.5ns
1.25ns
1.25ns
1.25ns
1.25ns
800MHz
800MHz
1066MHz
1066MHz
1066MHz
1333MHz
1333MHz
1333MHz
1600MHz
1600MHz
1600MHz
1600MHz
PART IDENTIFICATION
PART NO.
UG12U6400M8SU
REF. CYCLE
8K
SDRAM
PACKAGE
FBGA
PLATING
Gold
REVISION HISTORY
Dec 22, 2009
Rev - A
Product Brief Released.
Re-Tek- 1547
support@unigen.com
http://www.unigen.com,
D
EN
-9AB
-9BB
-9CB
-AAB
-ABB
-ACB
-BAB
-BBB
-BCB
-BDB
1
TI
AL
45388 Warm Springs Blvd. Fremont, CA. 94539
TEL: (510) 668-2088
FAX: (510)661-2788
Customer Comment Line: 1-800-826-0808

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ECCN code - EAR99 EAR99
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