PRELIMINARY
TECHNOLOGY, INC.
MT4LD(T)164A (X), MT8LD264A (X), MT16LD464A (X)
1, 2, 4 MEG x 64 DRAM MODULES
DRAM
MODULE
FEATURES
•
•
•
•
•
•
•
•
168-pin, dual-in-line memory module (DIMM)
Nonbuffered
High-performance CMOS silicon-gate process
Single +3.3V
±0.3V
power supply
All device pins are TTL-compatible
Refresh modes: RAS# ONLY, CAS#-BEFORE-RAS#
(CBR), HIDDEN
FAST PAGE MODE (FPM) or Extended Data-Out
(EDO) PAGE MODE access cycles
1,024-cycle refresh (10 row-, 10 column-addresses)
[MT4LD(T)164A (X)]
2,048-cycle refresh (11 row-, 10 column-addresses)
[MT8LD264A (X)]
2,048-cycle refresh (11 row-, 11 column-addresses)
[MT16LD464A (X)]
5V-tolerant inputs and I/Os (5.5V maximum V
IH
level)
Serial Presence-Detect (SPD)
1, 2, 4 MEG x 64
8, 16, 32 MEGABYTE, NONBUFFERED,
3.3V, EDO OR FAST PAGE MODE
PIN ASSIGNMENT (Front View)
168-Pin DIMM
(DE-9) 1 Meg x 64 SOJ version
(DE-11) 1 Meg x 64 TSOJ version
(DE-12) 2 Meg x 64 (shown), (DE-10) 4 Meg x 64
•
•
OPTIONS
• Timing
60ns access
70ns access
• Components
SOJ
TSOP (1 Meg x 64 only)
• Packages
168-pin DIMM (gold)
• Access Cycle
FAST PAGE MODE
EDO PAGE MODE
MARKING
-6
-7
D
DT
G
Blank
X
KEY TIMING PARAMETERS
EDO Operating Mode
SPEED
-6
-7
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
CAS
105ns
125ns
60ns
70ns
25ns
30ns
30ns
35ns
15ns
20ns
12ns
12ns
FPM Operating Mode
SPEED
-6
-7
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
RP
110ns
130ns
60ns
70ns
35ns
40ns
30ns
35ns
15ns
20ns
40ns
50ns
PIN # SYMBOL PIN #
1
Vss
43
2
DQ0
44
3
DQ1
45
4
DQ2
46
5
DQ3
47
6
Vcc
48
7
DQ4
49
8
DQ5
50
9
DQ6
51
10
DQ7
52
11
DQ8
53
12
Vss
54
13
DQ9
55
14
DQ10
56
15
DQ11
57
16
DQ12
58
17
DQ13
59
18
Vcc
60
19
DQ14
61
20
DQ15
62
21
NC
63
22
NC
64
23
Vss
65
24
NC
66
25
NC
67
26
Vcc
68
27
WE0#
69
28
CAS0#
70
29
CAS1#
71
30
RAS0#
72
31
OE0#
73
32
Vss
74
33
A0
75
34
A2
76
35
A4
77
36
A6
78
37
A8
79
38
NC*/A10
80
39
NC
81
40
Vcc
82
41
Vcc
83
42
RFU
84
*1 Meg x 64 version only
SYMBOL
Vss
OE2#
RAS2#
CAS2#
CAS3#
WE2#
Vcc
NC
NC
NC
NC
Vss
DQ16
DQ17
DQ18
DQ19
Vcc
DQ20
NC
RFU
NC
Vss
DQ21
DQ22
DQ23
Vss
DQ24
DQ25
DQ26
DQ27
Vcc
DQ28
DQ29
DQ30
DQ31
Vss
NC
NC
NC
SDA
SCL
Vcc
PIN #
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
SYMBOL
Vss
DQ32
DQ33
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
DQ40
Vss
DQ41
DQ42
DQ43
DQ44
DQ45
Vcc
DQ46
DQ47
NC
NC
Vss
NC
NC
Vcc
RFU
CAS4#
CAS5#
NC
RFU
Vss
A1
A3
A5
A7
A9
NC
NC
Vcc
RFU
RFU
PIN #
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
SYMBOL
Vss
RFU
NC
CAS6#
CAS7#
RFU
Vcc
NC
NC
NC
NC
Vss
DQ48
DQ49
DQ50
DQ51
Vcc
DQ52
NC
RFU
NC
Vss
DQ53
DQ54
DQ55
Vss
DQ56
DQ57
DQ58
DQ59
Vcc
DQ60
DQ61
DQ62
DQ63
Vss
NC
NC
SA0
SA1
SA2
Vcc
MT4LD(T)164A (X), MT8LD264A (X), MT16LD464A (X)
DM67.pm5 – Rev. 3/96
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1996,
Micron Technology, Inc.
PRELIMINARY
TECHNOLOGY, INC.
MT4LD(T)164A (X), MT8LD264A (X), MT16LD464A (X)
1, 2, 4 MEG x 64 DRAM MODULES
Returning RAS# HIGH terminates the FAST PAGE MODE
operation.
PART NUMBERS
PART NUMBER
MT4LD164AG-xx
MT4LD164AG-xx X
MT4LDT164AG-xx
MT4LDT164AG-xx X
MT8LD264AG-xx
MT8LD264AG-xx X
MT16LD464AG-xx
MT16LD464AG-xx X
DESCRIPTION
1 Meg x 64 FPM, SPD,
Nonbuffered, SOJ
1 Meg x 64 EDO, SPD,
Nonbuffered, SOJ
1 Meg x 64 FPM, SPD,
Nonbuffered, TSOP
1 Meg x 64 EDO, SPD,
Nonbuffered, TSOP
2 Meg x 64 FPM, SPD,
Nonbuffered, SOJ
2 Meg x 64 EDO, SPD,
Nonbuffered, SOJ
4 Meg x 64 FPM, SPD,
Nonbuffered, SOJ
EDO PAGE MODE
EDO PAGE MODE, designated by the “X” version, is an
accelerated FAST PAGE MODE cycle. The primary advan-
tage of EDO is the availability of data-out even after CAS#
goes back HIGH. EDO provides for CAS# precharge time
(
t
CP) to occur without the output data going invalid. This
elimination of CAS# output control provides for pipeline
READs.
FAST PAGE MODE modules have traditionally turned
the output buffers off (High-Z) with the rising edge of
CAS#. EDO-PAGE-MODE DRAMs operate similar to FAST
PAGE MODE DRAMs, except data will remain valid or
become valid after CAS# goes HIGH during READs, pro-
vided RAS# and OE# are held LOW. If OE# is pulsed while
RAS# and CAS# are LOW, data will toggle from valid data
to High-Z and back to the same valid data. If OE# is toggled
or pulsed after CAS# goes HIGH while RAS# remains
LOW, data will transition to and remain High-Z.
During an application, if the DQ outputs are wire OR’d,
OE# must be used to disable idle banks of DRAMs. Alter-
natively, pulsing WE# to the idle banks during CAS# HIGH
time will also High-Z the outputs. Independent of OE#
control, the outputs will disable after
t
OFF, which is refer-
enced from the rising edge of RAS# or CAS#, whichever
occurs last (reference the MT4LC4M4E8 DRAM data sheet
for additional information on EDO functionality).
4 Meg x 64 EDO, SPD,
Nonbuffered, SOJ
xx = speed, SPD = serial presence-detect
GENERAL DESCRIPTION
The MT4LD(T)164A (X), MT8LD264A (X) and
MT16LD464A (X) are randomly accessed 8MB, 16MB and
32MB solid-state memories organized in a x64 configura-
tion. During READ or WRITE cycles, each bit is uniquely
addressed through the 20/21/22 address bits, which are
entered 10/11 bits (A0 -A10) at RAS# time and 10/11 bits
(A0-A10) at CAS# time.
SERIAL PRESENCE-DETECT EEPROM
This module incorporates Serial Presence Detect (SPD).
The SPD function is implemented using a 2,048 bit EEPROM.
This nonvolatile storage device contains data programmed
by Micron that identifies the module type and various
DRAM organization and timing parameters. System READ/
WRITE operations to the EEPROM device occur via a
standard I
2
C bus using the DIMM’s SCL (clock) and SDA
(data) signals, together with SA(2:0) which provide the
EEPROM device address. The EEPROM device operates
with a Vcc of 3.3V
±0.3V.
FAST PAGE MODE
FAST PAGE MODE operations allow faster data opera-
tions (READ or WRITE) within a row-address-defined
page boundary. The FAST PAGE MODE cycle is always
initiated with a row-address strobed-in by RAS# followed
by a column-address strobed-in by CAS#. CAS# may be
toggled-in by holding RAS# LOW and strobing-in different
column-addresses, thus executing faster memory cycles.
MT4LD(T)164A (X), MT8LD264A (X), MT16LD464A (X)
DM67.pm5 – Rev. 3/96
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1996,
Micron Technology, Inc.
PRELIMINARY
TECHNOLOGY, INC.
MT4LD(T)164A (X), MT8LD264A (X), MT16LD464A (X)
1, 2, 4 MEG x 64 DRAM MODULES
FUNCTIONAL BLOCK DIAGRAM
MT4LD(T)164A (X) (8MB)
DQ0
DQ15
DQ16
DQ31
16
16
DQ1 - 16
DQ1 - 16
WE#
U2
OE#
RAS#
LCAS#
UCAS# A0–A10
WE0#
OE0#
RAS0#
CAS0#
CAS1#
CAS2#
CAS3#
A0-A10
WE#
U1
OE#
RAS#
LCAS#
UCAS# A0–A10
11
11
DQ32 DQ47
DQ48
11
DQ63
16
16
DQ1 - 16
DQ1 - 16
WE#
U4
OE#
RAS#
LCAS#
UCAS# A0–A10
WE2#
OE2#
RAS2#
CAS4#
CAS5#
CAS6#
CAS7#
WE#
U3
OE#
RAS#
LCAS#
UCAS# A0–A10
11
11
SERIAL PD
SCL
A0
SA0
A1
SA1
A2
SA2
SDA
U1-U4 = MT4LC1M16C3 FAST PAGE MODE
U1-U4 = MT4LC1M16E5 EDO PAGE MODE
MT4LD(T)164A (X), MT8LD264A (X), MT16LD464A (X)
DM67.pm5 – Rev. 3/96
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1996,
Micron Technology, Inc.
PRELIMINARY
TECHNOLOGY, INC.
MT4LD(T)164A (X), MT8LD264A (X), MT16LD464A (X)
1, 2, 4 MEG x 64 DRAM MODULES
FUNCTIONAL BLOCK DIAGRAM
MT8LD264A (X) (16MB)
DQ0 DQ7
DQ8 DQ15
DQ16 DQ23
DQ24 DQ31
DQ1 - 8
WE#
U1
OE#
RAS#
CAS# A0–A10
11
DQ1 - 8
WE#
U2
OE#
RAS#
CAS# A0–A10
11
DQ1 - 8
WE#
U3
OE#
RAS#
CAS# A0–A10
11
DQ1 - 8
WE#
U4
OE#
RAS#
CAS# A0–A10
11
WE0#
OE0#
RAS0#
CAS0#
CAS1#
CAS2#
CAS3#
A0-A10
11
DQ32 DQ39
DQ40 DQ47
DQ48 DQ55
DQ56 DQ63
WE2#
OE2#
RAS2#
CAS4#
CAS5#
CAS6#
CAS7#
DQ1 - 8
WE#
U5
OE#
RAS#
CAS# A0–A10
11
DQ1 - 8
WE#
U6
OE#
RAS#
CAS# A0–A10
11
DQ1 - 8
WE#
U7
OE#
RAS#
CAS# A0–A10
11
DQ1 - 8
WE#
U8
OE#
RAS#
CAS# A0–A10
11
SERIAL PD
SCL
A0
A1
A2
SA0 SA1 SA2
SDA
U1-U8 = MT4LC2M8B1 FAST PAGE MODE
U1-U8 = MT4LC2M8E7 EDO PAGE MODE
FUNCTIONAL BLOCK DIAGRAM
MT16LD464A (X) (32MB)
DQ0
DQ3
DQ4
DQ7
DQ8
DQ11
DQ12
DQ15
DQ16
DQ19
DQ20
DQ23
DQ24
DQ27
DQ28
DQ31
DQ1 - 4
DQ1 - 4
WE#
WE#
U2
OE#
RAS#
CAS# A0–A10
OE#
DQ1 - 4
WE#
U3
OE#
RAS#
CAS# A0–A10
DQ1 - 4
WE#
U4
OE#
RAS#
CAS# A0–A10
DQ1 - 4
WE#
U5
OE#
RAS#
CAS# A0–A10
DQ1 - 4
WE#
U6
OE#
RAS#
CAS# A0–A10
DQ1 - 4
WE#
U7
OE#
RAS#
CAS# A0–A10
DQ1 - 4
U8
RAS#
CAS# A0–A10
WE0#
OE0#
RAS0#
CAS0#
CAS1#
CAS2#
CAS3#
A0-A10
11
WE#
U1
OE#
RAS#
CAS# A0–A10
11
11
11
11
11
11
11
11
DQ32
DQ35
DQ36
DQ39
DQ40
DQ43
DQ44
DQ47
DQ48
DQ51
DQ52
DQ55
DQ56
DQ59
DQ60
DQ63
DQ1 - 4
DQ1 - 4
WE#
WE#
U10
OE#
RAS#
CAS# A0–A10
OE#
DQ1 - 4
WE#
U11
OE#
DQ1 - 4
WE#
U12
OE#
DQ1 - 4
WE#
U13
OE#
RAS#
CAS# A0–A10
DQ1 - 4
WE#
U14
OE#
RAS#
CAS# A0–A10
DQ1 - 4
WE#
U15
OE#
RAS#
CAS# A0–A10
DQ1 - 4
U16
RAS#
CAS# A0–A10
WE2#
OE2#
RAS2#
CAS4#
CAS5#
CAS6#
CAS7#
WE#
U9
OE#
RAS#
CAS# A0–A10
RAS#
CAS# A0–A10
RAS#
CAS# A0–A10
11
11
11
11
11
11
11
11
SERIAL PD
SCL
A0
A1
A2
SA0 SA1 SA2
SDA
U1-U16 = MT4LC4M4B1 FAST PAGE MODE
U1-U16 = MT4LC4M4E8 EDO PAGE MODE
MT4LD(T)164A (X), MT8LD264A (X), MT16LD464A (X)
DM67.pm5 – Rev. 3/96
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1996,
Micron Technology, Inc.
PRELIMINARY
TECHNOLOGY, INC.
MT4LD(T)164A (X), MT8LD264A (X), MT16LD464A (X)
1, 2, 4 MEG x 64 DRAM MODULES
SERIAL PRESENCE-DETECT EEPROM
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1) (V
CC
= +3.3V
±0.3V)
PARAMETER/CONDITION
Supply Voltage
Input High (Logic 1) Voltage, all inputs
Input Low (Logic 0) Voltage, all inputs
OUTPUT LOW VOLTAGE, I
OUT
= 3mA
INPUT LEAKAGE CURRENT, V
IN
= GND to V
CC
OUTPUT LEAKAGE CURRENT, V
OUT
= GND to V
CC
STANDBY CURRENT
SCL = SDA = V
CC
-0.3V, All other inputs = GND or V
CC
3.3V +10%
POWER SUPPLY CURRENT
SCL clock frequency = 100 KHz
SYMBOL
V
CC
V
IH
V
IL
V
OL
I
LI
I
LO
I
SB
I
CC
MIN
3.0
-1.0
MAX
3.6
V
CC
×
.3
0.4
10
10
30
2
UNITS
V
V
V
V
µA
µA
µA
mA
NOTES
V
CC
×
.7 V
CC
×
.5
SERIAL PRESENCE-DETECT EEPROM
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 1) (V
CC
= +3.3V
±0.3V)
AC CHARACTERISTICS
PARAMETER/CONDITION
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
SDA and SCL fall time
Data-in hold time
Start condition hold time
Clock HIGH period
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
SDA and SCL rise time
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
SYMBOL
t
AA
t
BUF
t
DH
t
F
t
HD:DAT
t
HD:STA
t
HIGH
t
I
t
LOW
t
R
t
SCL
t
SU:DAT
t
SU:STA
t
SU:STO
t
WR
MIN
0.3
4.7
300
0
4
4
MAX
3.5
300
100
4.7
1
100
250
4.7
4.7
10
UNITS
µs
µs
ns
ns
µs
µs
µs
ns
µs
µs
KHz
ns
µs
µs
ms
NOTES
31
MT4LD(T)164A (X), MT8LD264A (X), MT16LD464A (X)
DM67.pm5 – Rev. 3/96
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1996,
Micron Technology, Inc.