DATA SHEET
MOS FIELD EFFECT TRANSISTOR
µ
PA2713GR
SWITCHING
P-CHANNEL POWER MOS FET
DESCRIPTION
The
µ
PA2713GR is P-channel MOS Field Effect Transistor
designed for power management applications of notebook
computers and Li-ion battery protection circuit.
PACKAGE DRAWING (Unit: mm)
8
5
1, 2, 3 : Source
4
: Gate
5, 6, 7, 8: Drain
FEATURES
•
Low on-state resistance
R
DS(on)1
= 16 mΩ MAX. (V
GS
=
−10
V, I
D
=
−4.0
A)
R
DS(on)2
= 25 mΩ MAX. (V
GS
=
−4.5
V, I
D
=
−4.0
A)
R
DS(on)3
= 30 mΩ MAX. (V
GS
=
−4.0
V, I
D
=
−4.0
A)
•
Low C
iss
: C
iss
= 1600 pF TYP.
•
Small and surface mount package (Power SOP8)
1
4
5.37 MAX.
+0.10
–0.05
6.0 ±0.3
4.4
0.8
1.8 MAX.
1.44
0.15
0.05 MIN.
0.5 ±0.2
0.10
ORDERING INFORMATION
PART NUMBER
PACKAGE
Power SOP8
1.27 0.78 MAX.
0.40
+0.10
–0.05
0.12 M
µ
PA2713GR
ABSOLUTE MAXIMUM RATINGS (T
A
= 25°C, All terminals are connected.)
Drain to Source Voltage (V
GS
= 0 V)
Gate to Source Voltage (V
DS
= 0 V)
Drain Current (DC)
Drain Current (pulse)
Note1
Note2
Note3
V
DSS
V
GSS
I
D(DC)
I
D(pulse)
P
T1
P
T2
T
ch
T
stg
−30
m20
m8
m32
2
2
150
−55
to +150
8
6.4
V
V
A
A
W
W
°C
°C
A
mJ
Source
Gate
Total Power Dissipation
Total Power Dissipation
Channel Temperature
Storage Temperature
EQUIVALENT CIRCUIT
Drain
Single Avalanche Current
Single Avalanche Energy
Notes 1.
2.
3.
4.
Note4
Note4
I
AS
E
AS
Body
Diode
PW
≤
10
µ
s, Duty Cycle
≤
1%
2
Mounted on ceramic substrate of 1200 mm x 2.2 mm
Mounted on a glass epoxy board (1 inch x 1 inch x 0.8 mm), PW = 10 sec
Starting T
ch
= 25°C, V
DD
=
−15
V, R
G
= 25
Ω,
L = 100
µ
H, V
GS
=
−20 →
0 V
Remark
Strong electric field, when exposed to this device, can cause destruction of the gate oxide and ultimately
degrade the device operation. Steps must be taken to stop generation of static electricity as much as
possible, and quickly dissipate it once, when it has occurred.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. G15981EJ1V0DS00 (1st edition)
Date Published January 2003 NS CP(K)
Printed in Japan
2002
µ
PA2713GR
ELECTRICAL CHARACTERISTICS (T
A
= 25°C, All terminals are connected.)
CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate Leakage Current
Gate Cut-off Voltage
Note
Forward Transfer Admittance
Note
Drain to Source On-state Resistance
Note
SYMBOL
I
DSS
I
GSS
V
GS(off)
| y
fs
|
R
DS(on)1
R
DS(on)2
R
DS(on)3
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Total Gate Charge
Gate to Source Charge
Gate to Drain Charge
Body Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
Q
G
Q
GS
Q
GD
V
F(S-D)
t
rr
Q
rr
V
DD
=
−
24 V
V
GS
=
−
10 V
I
D
= 8 A
I
F
= 8 A, V
GS
= 0 V
I
F
= 8 A, V
GS
= 0 V
di/dt = 100 A/
µ
s
TEST CONDITIONS
V
DS
=
−
30 V, V
GS
= 0 V
V
GS
=
m
20 V, V
DS
= 0 V
V
DS
=
−
10 V, I
D
=
−
1 mA
V
DS
=
−
10 V, I
D
=
−
4.0 A
V
GS
=
−
10 V, I
D
=
−
4.0 A
V
GS
=
−
4.5 V, I
D
=
−
4.0 A
V
GS
=
−
4.0 V, I
D
=
−
4.0 A
V
DS
=
−
10 V
V
GS
= 0 V
f = 1 MHz
V
DD
=
−
15 V, I
D
=
−
4.0 A
V
GS
=
−
10 V
R
G
= 10
Ω
MIN.
TYP.
MAX.
UNIT
−
1
m
100
−
1.0
6
14
12
17
20
1600
450
270
9
15
83
43
35
4.8
10
0.81
43
29
16
25
30
µ
A
nA
V
S
mΩ
mΩ
mΩ
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
ns
nC
−
2.5
Note
Pulsed: PW
≤
350
µ
s, Duty Cycle
≤
2%
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
R
G
= 25
Ω
PG.
V
GS
=
−20 →
0 V
50
Ω
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
L
V
DD
PG.
R
G
V
GS(−)
R
L
V
DD
V
DS(−)
90%
90%
10%
10%
V
GS
Wave Form
0
10%
V
GS
90%
BV
DSS
I
AS
I
D
V
DD
V
DS
V
GS(−)
0
V
DS
V
DS
Wave Form
0
t
d(on)
t
on
τ
τ
= 1
µ
s
Duty Cycle
≤
1%
t
r
t
d(off)
t
off
t
f
Starting T
ch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
I
G
=
−2
mA
PG.
50
Ω
R
L
V
DD
2
Data Sheet G15981EJ1V0DS
µ
PA2713GR
TYPICAL CHARACTERISTICS (T
A
= 25°C, All terminals are connected.)
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
dT - Percentage of Rated Power - %
120
2.8
TOTAL POWER DISSIPATION vs.
AMBIENT TEMPERATURE
P
T
- Total Power Dissipation - W
Mounted on ceramic substrate of
1200 mm
2
x 2.2 mm
100
80
60
40
20
0
0
25
50
75
100
125
150
175
2.4
2
1.6
1.2
0.8
0.4
0
0
25
50
75
100
125
150
175
T
A
- Ambient Temperature -
°C
T
A
- Ambient Temperature -
°C
FORWARD BIAS SAFE OPERATING AREA
- 100
I
D(pulse)
PW = 100
µs
I
D
- Drain Current - A
- 10
I
D(DC)
1 ms
-1
R
DS(on)
Lim ited
10 m s
(V
GS
= 10 V)
100 m s
Power Dissipation Lim ited
- 0.1
Single pulse
M ounted on ceram ic substrate of
1200 m m
2
x 2.2 m m
DC
- 0.01
- 0.01
- 0.1
-1
- 10
- 100
V
DS
- Drain to Source Voltage - V
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
1000
r
th(t)
- Transient Thermal Resistance -
°C/W
R
th(ch-A)
= 62.5°C/W
100
10
1
0.1
Single pulse
2
Mounted on ceramic substrate of 1200 mm x 2.2 mm
0.01
100
µ
1m
10 m
100 m
1
10
100
1000
PW - Pulse Width - s
Data Sheet G15981EJ1V0DS
3
µ
PA2713GR
DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE
- 40
Pulsed
−4.5
V
FORWARD TRANSFER CHARACTERISTICS
- 100
V
DS
=
−10
V
Pulsed
I
D
- Drain Current - A
- 30
I
D
- Drain Current - A
V
GS
=
−10
V
−4.0
V
- 10
- 20
-1
T
ch
=
−55°C
25°C
75°C
150°C
- 10
- 0.1
0
0
- 0.2
- 0.4
- 0.6
- 0.8
-1
- 0.01
0
-1
-2
-3
-4
-5
V
DS
- Drain to Source Voltage - V
V
GS
- Gate to Source Voltage - V
GATE CUT-OFF VOLTAGE vs.
CHANNEL TEMPERATURE
-3
FORWARD TRANSFER ADMITTANCE vs.
DRAIN CURRENT
| y
fs
| - Forward Transfer Admittance - S
100
V
DS
=
−10
V T
ch
=
−55°C
Pulsed
25°C
75°C
150°C
V
GS(off)
- Gate Cut-off Voltage - V
- 2.5
-2
- 1.5
-1
- 0.5
0
-50
V
DS
=
−10
V
I
D
=
−1
mA
10
1
0
50
100
150
0.1
- 0.1
-1
- 10
- 100
T
ch
- Channel Temperature -
°C
I
D
- Drain Current - A
R
DS(on)
- Drain to Source On-state Resistance - mΩ
40
35
30
25
20
15
10
5
R
DS(on)
- Drain to Source On-state Resistance - mΩ
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
DRAIN CURRENT
Pulsed
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE
40
Pulsed
30
V
GS
=
−4.0
V
−4.5
V
20
I
D
=
−4.0
A
−10
V
10
0
- 0.1
0
0
-5
- 10
- 15
- 20
-1
- 10
- 100
I
D
- Drain Current - A
V
GS
- Gate to Source Voltage - V
4
Data Sheet G15981EJ1V0DS
µ
PA2713GR
R
DS(on)
- Drain to Source On-state Resistance - mΩ
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CHANNEL TEMPERATURE
30
25
20
−4.5
V
I
D
=
−4.0
A
Pulsed
CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE
10000
C
iss
, C
oss
, C
rss
- Capacitance - pF
V
GS
=
−4.0
V
V
GS
= 0 V
f = 1 M Hz
C
iss
1000
C
oss
15
−10
V
10
5
0
-50
0
50
100
150
100
C
rss
10
- 0.01
- 0.1
-1
- 10
- 100
T
ch
- Channel Temperature - °C
V
DS
- Drain to Source Voltage - V
SWITCHING CHARACTERISTICS
1000
DYNAMIC INPUT/OUTPUT CHARACTERISTICS
- 30
- 15
V
DS
- Drain to Source Voltage - V
100
t
d(off)
t
f
t
r
- 20
V
DD
=
−24
V
−15
V
−6
V
- 10
V
GS
10
t
d(on)
- 10
-5
V
DS
1
- 0.1
0
-1
- 10
- 100
0
0
10
20
30
40
I
D
- Drain Current - A
Q
G
- Gate Charge - nC
SOURCE TO DRAIN DIODE
FORWARD VOLTAGE
1000
Pulsed
REVERSE RECOVERY TIME vs.
DIODE FORWARD CURRENT
1000
di/dt = 100 A/µs
V
GS
= 0 V
100
t
rr
- Reverse Recovery Time - ns
I
F
- Diode Forward Current - A
100
10
V
GS
=
−10
V
0V
1
10
0.1
0.01
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1
0.1
1
10
100
V
F(S-D)
- Source to Drain Voltage - V
I
F
- Diode Forward Current - A
Data Sheet G15981EJ1V0DS
5
V
GS
- Gate to Source Voltage - V
t
d(on)
, t
r
, t
d(off)
, t
f
- Switching Time - ns
V
DD
=
−15
V
V
GS
=
−10
V
R
G
= 10
Ω
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