S71NS64NA0BJWSW3 datasheet, PDF

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S71NS64NA0BJWSW3: DescriptionMemory Circuit, 4MX16, CMOS, PBGA44, 9.20 X 8 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-44; Categorystorage storage; File Size3MB，113 Pages; ManufacturerSPANSION; Websitehttp://www.spansion.com/; Environmental Compliance

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S71NS64NA0BJWSW3 Overview

Memory Circuit, 4MX16, CMOS, PBGA44, 9.20 X 8 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-44

S71NS64NA0BJWSW3 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	SPANSION
Parts packaging code	BGA
package instruction	TFBGA,
Contacts	44
Reach Compliance Code	compliant
Other features	PSRAM IS ORGANIZED AS 1M X 16; SYNCHRONOUS BURST MODE ALSO POSSIBLE
JESD-30 code	R-PBGA-B44
JESD-609 code	e1
length	9.2 mm
memory density	67108864 bit
Memory IC Type	MEMORY CIRCUIT
memory width	16
Humidity sensitivity level	3
Number of functions	1
Number of terminals	44
word count	4194304 words
character code	4000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-25 °C
organize	4MX16
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	1.95 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	TIN SILVER COPPER
Terminal form	BALL
Terminal pitch	0.5 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	40
width	8 mm

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S71NS128NA0/S71NS064NA0 Based MCPs

Stacked Multi-Chip Product (MCP) MirrorBit™ Flash Memory

and pSRAM 128 Mb (8M x 16-bit) and 64 Mb (4M x 16-Bit),

110 nm CMOS 1.8 Volt-only, Multiplexed, Simultaneous Read/

Write, Burst Mode Flash Memory with

16 Mb (1M x 16-Bit) pSRAM

Data Sheet

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Publication Number

S71NS128_064NA0_00

Revision

Amendment

Issue Date

September 23, 2005

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S71NS128NA0/S71NS064NA0 Based MCPs

S71NS128_064NA0_00_A1 September 23, 2005

A d v a n c e

I n f o r m a t i o n

Contents

S71NS128NA0/S71NS064NA0 Based MCPs . . . . . . . . . . . . . . . . . . . . . . . . 1

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

MCP Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

S71NS128NA0, 44-ball Very-Thin FBGA (NLB044) Pinout, NS128N + 16 PSRAM................................................................9

S71NS064NA0, 44-ball Very-Thin FBGA (NLD044) Pinout, NS064N + 16 PSRAM .......................................................... 10

Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Order Number .........................................................................................................................................................................................12

Physical Dimension — S71NS128NA0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

NLB044, 44-Ball Very Thin Fine-Pitch Ball Grid Array (FBGA) 9.2 x 8 mm Package .......................................................13

Physical Dimension — S71NS064NA0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

NLD044, 44-Ball Very Thin Fine-pitch Ball Grid Array (BGA) 7.7 x 6.2 mm....................................................................... 14

S29NSxxxN MirrorBit

Flash Family . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Block Diagram of Simultaneous Operation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

VersatileIO™ (V

) Control.................................................................................................................................................................24

Requirements for Asynchronous Read Operation (Non-Burst)..............................................................................................24

Requirements for Synchronous (Burst) Read Operation...........................................................................................................25

Continuous Burst .........................................................................................................................................................................25

8-, 16-, and 32-Word Linear Burst with Wrap Around ....................................................................................................27

8-, 16-, and 32-Word Linear Burst without Wrap Around .............................................................................................27

Programmable Wait State................................................................................................................................................................... 28

Configuration Register ......................................................................................................................................................................... 28

Handshaking Feature............................................................................................................................................................................. 28

Simultaneous Read/Write Operations with Zero Latency ....................................................................................................... 28

Writing Commands/Command Sequences.................................................................................................................................... 28

Accelerated Program and Erase Operations................................................................................................................................. 28

Write Buffer Programming Operation............................................................................................................................................ 29

Autoselect Mode.....................................................................................................................................................................................30

Advanced Sector Protection and Unprotection............................................................................................................................30

Sector Protection.....................................................................................................................................................................................31

Persistent Sector Protection ................................................................................................................................................................31

Persistent Protection Bit (PPB) ................................................................................................................................................32

Persistent Protection Bit Lock (PPB Lock Bit) in Persistent Sector Protection Mode ..........................................32

Dynamic Protection Bit (DYB) ................................................................................................................................................32

Persistent Sector Protection Mode Lock Bit..................................................................................................................................33

Password Sector Protection................................................................................................................................................................34

64-bit Password .......................................................................................................................................................................................34

Password Mode Lock Bit......................................................................................................................................................................34

Persistent Protection Bit Lock (PPB Lock Bit) in Password Sector Protection Mode......................................................35

Hardware Data Protection Mode......................................................................................................................................................35

Write Protect (WP#) .................................................................................................................................................................35

WP# Boot Sector Protection .............................................................................................................................................................35

Low VCC Write Inhibit ........................................................................................................................................................................36

S71NS128NA0/S71NS064NA0 Based MCPs

S71NS128_064NA0_00_A1 September 23, 2005

A d v a n c e

I n f o r m a t i o n

Write Pulse “Glitch” Protection ........................................................................................................................................................36

Logical Inhibit............................................................................................................................................................................................36

Power-Up Write Inhibit .............................................................................................................................................................36

Lock Register............................................................................................................................................................................................36

Standby Mode .........................................................................................................................................................................................37

Automatic Sleep Mode ..........................................................................................................................................................................37

RESET#: Hardware Reset Input .........................................................................................................................................................37

Power-up and Power-down Sequencing .....................................................................................................................37

Output Disable Mode............................................................................................................................................................................37

SecSi™ (Secured Silicon) Sector Flash Memory Region...............................................................................................................37

Factory Locked: Factor SecSi Sector Programmed and Protected At the Factory .................................................38

Customer SecSi Sector ...............................................................................................................................................................38

Common Flash Memory Interface (CFI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Reading Array Data.................................................................................................................................................................................51

Set Configuration Register Command Sequence...........................................................................................................................51

Read Configuration Register Command Sequence .......................................................................................................................51

Read Mode Setting .......................................................................................................................................................................52

Programmable Wait State Configuration .............................................................................................................................52

Programmable Wait State .........................................................................................................................................................52

Handshaking ...................................................................................................................................................................................53

Burst Length Configuration .......................................................................................................................................................53

Burst Wrap Around ....................................................................................................................................................................53

RDY Configuration ......................................................................................................................................................................53

RDY Polarity ..................................................................................................................................................................................54

Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Reset Command......................................................................................................................................................................................55

Autoselect Command Sequence .......................................................................................................................................................57

Enter SecSi™ Sector/Exit SecSi Sector Command Sequence.....................................................................................................57

Unlock Bypass Command Sequence ..................................................................................................................................... 58

Program Command Sequence ........................................................................................................................................................... 58

Program Command Sequence ................................................................................................................................................. 58

Program Command Sequence (Unlock Bypass Mode) .................................................................................................... 58

Accelerated Program............................................................................................................................................................................ 58

Write Buffer Programming Command Sequence .........................................................................................................................59

Chip Erase Command Sequence .........................................................................................................................................................61

Chip Erase Command Sequence ..............................................................................................................................................61

Sector Erase Command Sequence.....................................................................................................................................................62

Sector Erase Command Sequence ..........................................................................................................................................62

Accelerated Sector Erase ..........................................................................................................................................................63

Erase Suspend/Erase Resume Commands...................................................................................................................................... 64

Program Suspend/Program Resume Commands ......................................................................................................................... 64

Lock Register Command Set Definitions ........................................................................................................................................65

Password Protection Command Set Definitions ..........................................................................................................................65

Non-Volatile Sector Protection Command Set Definitions ..................................................................................................... 66

Global Volatile Sector Protection Freeze Command Set.......................................................................................................... 68

Volatile Sector Protection Command Set...................................................................................................................................... 68

Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

DQ7: Data# Polling ................................................................................................................................................................................74

RDY: Ready .............................................................................................................................................................................................76

DQ6: Toggle Bit I....................................................................................................................................................................................76

DQ2: Toggle Bit II...................................................................................................................................................................................76

Reading Toggle Bits DQ6/DQ2 ......................................................................................................................................................... 78

DQ5: Exceeded Timing Limits ........................................................................................................................................................... 78

DQ3: Sector Erase Start Timeout State Indicator........................................................................................................................79

September 23, 2005 S71NS128_064NA0_00_A1

S71NS128NA0/S71NS064NA0 Based MCPs

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