XCV812E-8BGG560C datasheet, PDF

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XCV812E-8BGG560C: DescriptionField Programmable Gate Array, 4704 CLBs, 254016 Gates, 416MHz, CMOS, PBGA560, PLASTIC, BGA-560; CategoryProgrammable logic devices Programmable logic; File Size1MB，118 Pages; ManufacturerXILINX; Websitehttps://www.xilinx.com/; Environmental Compliance

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XCV812E-8BGG560C Overview

Field Programmable Gate Array, 4704 CLBs, 254016 Gates, 416MHz, CMOS, PBGA560, PLASTIC, BGA-560

XCV812E-8BGG560C Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	XILINX
Parts packaging code	BGA
package instruction	LBGA,
Contacts	560
Reach Compliance Code	compliant
ECCN code	3A001.A.7.A
maximum clock frequency	416 MHz
Combined latency of CLB-Max	0.4 ns
JESD-30 code	S-PBGA-B560
JESD-609 code	e1
length	42.5 mm
Humidity sensitivity level	3
Configurable number of logic blocks	4704
Equivalent number of gates	254016
Number of terminals	560
Maximum operating temperature	70 °C
Minimum operating temperature
organize	4704 CLBS, 254016 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE
Peak Reflow Temperature (Celsius)	260
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	1.7 mm
Maximum supply voltage	1.89 V
Minimum supply voltage	1.71 V
Nominal supply voltage	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Silver/Copper (Sn95.5Ag4.0Cu0.5)
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	42.5 mm

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— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —

Virtex™-E 1.8 V Extended Memory

Field Programmable Gate Arrays

DS025-1 (v3.0) March 21, 2014

Production Product Specification

Features

•

Fast, Extended Block RAM, 1.8 V FPGA Family

- 560 Kb and 1,120 Kb embedded block RAM

- 130 MHz internal performance (four LUT levels)

- PCI compliant 3.3 V, 32/64-bit, 33/66-MHz

Sophisticated SelectRAM+™ Memory Hierarchy

- 294 Kb of internal configurable distributed RAM

- Up to 1,120 Kb of synchronous internal block RAM

- True Dual-Port block RAM

- Memory bandwidth up to 2.24 Tb/s (equivalent

bandwidth of over 100 RAMBUS channels)

- Designed for high-performance Interfaces to

external memories

200 MHz ZBT* SRAMs

200 Mb/s DDR SDRAMs

Highly Flexible SelectIO+™ Technology

- Supports 20 high-performance interface standards

- Up to 556 singled-ended I/Os or up to 201

differential I/O pairs for an aggregate bandwidth of

>100 Gb/s

Complete Industry-Standard Differential Signalling

Support

- LVDS (622 Mb/s), BLVDS (Bus LVDS), LVPECL

- Al I/O signals can be input, output, or bi-directional

* ZBT is a trademark of Integrated Device Technology, Inc.

•

LVPECL and LVDS clock inputs for 300+ MHz

clocks

Proprietary High-Performance SelectLink™

Technology

- 80 Gb/s chip-to-chip communication link

- Support for Double Data Rate (DDR) interface

- Web-based HDL generation methodology

Eight Fully Digital Delay-Locked Loops (DLLs)

IEEE 1149.1 boundary-scan logic

Supported by Xilinx Foundation Series™ and Alliance

Series™ Development Systems

- Internet Team Design (Xilinx iTD™) tool ideal for

million-plus gate density designs

- Wide selection of PC or workstation platforms

SRAM-based In-System Configuration

- Unlimited re-programmability

Advanced Packaging Options

- 1.0 mm FG676 and FG900

- 1.27 mm BG560

0.18

μm

6-layer Metal Process with Copper

Interconnect

100% Factory Tested

Introduction

The Virtex™-E Extended Memory (Virtex-EM) family of

FPGAs is an extension of the highly successful Virtex-E

family architecture. The Virtex-EM family (devices shown in

Table 1)

includes all of the features of Virtex-E, plus addi-

tional block RAM, useful for applications such as network

switches and high-performance video graphic systems.

Xilinx developed the Virtex-EM product family to enable

customers to design systems requiring high memory band-

width, such as 160 Gb/s network switches. Unlike traditional

ASIC devices, this family also supports fast time-to-market

delivery, because the development engineering is already

completed. Just complete the design and program the

device. There is no NRE, no silicon production cycles, and no

additional delays for design re-work. In addition, designers

can update the design over a network at any time, providing

product upgrades or updates to customers even sooner.

The Virtex-EM family is the result of more than fifteen years

of FPGA design experience. Xilinx has a history of support-

ing customer applications by providing the highest level of

logic, RAM, and features available in the industry. The Vir-

tex-EM family, first FPGAs to deploy copper interconnect,

offers the performance and high memory bandwidth for

advanced system integration without the initial investment,

long development cycles, and inventory risk expected in tra-

ditional ASIC development.

http://www.xilinx.com/legal.htm.

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS025-1 (v3.0) March 21, 2014

Production Product Specification

www.xilinx.com

Module 1 of 4

XCV812E-8BGG560C Related Products

	XCV812E-8BGG560C	XCV812E-6BGG560I
Description	Field Programmable Gate Array, 4704 CLBs, 254016 Gates, 416MHz, CMOS, PBGA560, PLASTIC, BGA-560	Field Programmable Gate Array, 4704 CLBs, 254016 Gates, 357MHz, CMOS, PBGA560, PLASTIC, BGA-560
Is it lead-free?	Lead free	Lead free
Is it Rohs certified?	conform to	conform to
Maker	XILINX	XILINX
Parts packaging code	BGA	BGA
package instruction	LBGA,	LBGA,
Contacts	560	560
Reach Compliance Code	compliant	compliant
ECCN code	3A001.A.7.A	3A001.A.7.A
maximum clock frequency	416 MHz	357 MHz
Combined latency of CLB-Max	0.4 ns	0.47 ns
JESD-30 code	S-PBGA-B560	S-PBGA-B560
JESD-609 code	e1	e1
length	42.5 mm	42.5 mm
Humidity sensitivity level	3	3
Configurable number of logic blocks	4704	4704
Equivalent number of gates	254016	254016
Number of terminals	560	560
Maximum operating temperature	70 °C	85 °C
organize	4704 CLBS, 254016 GATES	4704 CLBS, 254016 GATES
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LBGA	LBGA
Package shape	SQUARE	SQUARE
Package form	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE
Peak Reflow Temperature (Celsius)	260	260
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified	Not Qualified
Maximum seat height	1.7 mm	1.7 mm
Maximum supply voltage	1.89 V	1.89 V
Minimum supply voltage	1.71 V	1.71 V
Nominal supply voltage	1.8 V	1.8 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	COMMERCIAL	INDUSTRIAL
Terminal surface	Tin/Silver/Copper (Sn95.5Ag4.0Cu0.5)	Tin/Silver/Copper (Sn95.5Ag4.0Cu0.5)
Terminal form	BALL	BALL
Terminal pitch	1.27 mm	1.27 mm
Terminal location	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	30	30
width	42.5 mm	42.5 mm

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