DATA SHEET
MOS FIELD EFFECT TRANSISTOR
µ
PA1851
P-CHANNEL MOS FIELD EFFECT TRANSISTOR
FOR SWITCHING
DESCRIPTION
The
µ
PA1851 is a switching device which can be
driven directly by a 4.0
-
V power source.
The
µ
PA1851 features a low on-state resistance and
excellent switching characteristics, and is suitable for
applications such as power switch of portable machine
and so on.
8
PACKAGE DRAWING (Unit : mm)
5
1
2, 3
4
5
6, 7
8
:Drain1
:Source1
:Gate1
:Gate2
:Source2
:Drain2
1.2 MAX.
1.0±0.05
0.25
3°
+5°
–3°
0.1±0.05
0.5
0.6
+0.15
–0.1
FEATURES
•
Can be driven by a 4.0-V power source
•
Low on-state resistance
R
DS(on)1
= 105 mΩ MAX. (V
GS
= –10 V, I
D
= –1.5 A)
R
DS(on)2
= 210 mΩ MAX. (V
GS
= –4.5 V, I
D
= –1.5 A)
R
DS(on)3
= 250 mΩ MAX. (V
GS
= –4.0 V, I
D
= –1.5 A)
•
Built-in G-S protection diode against ESD
1
4
0.145 ±0.055
3.15 ±0.15
3.0 ±0.1
6.4 ±0.2
4.4 ±0.1
1.0 ±0.2
ORDERING INFORMATION
PART NUMBER
PACKAGE
Power TSSOP8
0.65
0.27
+0.03
–0.08
0.8 MAX.
µ
PA1851GR-9JG
0.1
0.10 M
ABSOLUTE MAXIMUM RATINGS (T
A
= 25°C)
Drain to Source Voltage
Gate to Source Voltage
Drain Current (DC)
Drain Current (pulse)
Note1
Note2
V
DSS
V
GSS
I
D(DC)
I
D(pulse)
P
T
T
ch
T
stg
–20
–20/+5
V
V
A
A
W
°C
°C
Gate
Protection
Diode
Gate1
EQUIVALENT CIRCUIT
Drain1
Drain2
!
2.5
!
10
2.0
150
–55 to +150
Total Power Dissipation
Channel Temperature
Storage Temperature
Body
Diode
Gate2
Body
Diode
Notes 1.
PW
≤
10
µ
s, Duty Cycle
≤
1 %
2
2.
Mounted on ceramic substrate of 50 cm x 1.1 mm
Remark
Source1
Gate
Protection
Diode
Source2
The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage
exceeding the rated voltage may be applied to this device.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No.
D12733EJ2V0DS00 (2nd edition)
Date Published February 2000 NS CP(K)
Printed in Japan
The mark
5
shows major revised points.
©
1997, 2000
µ
PA1851
5
ELECTRICAL CHARACTERISTICS (T
A
= 25 °C)
CHARACTERISTICS
Drain Cut-off Current
Gate Leakage Current
Gate Cut-off Voltage
Forward Transfer Admittance
Drain to Source On-state Resistance
SYMBOL
I
DSS
I
GSS
V
GS(off)
| y
fs
|
R
DS(on)1
R
DS(on)2
R
DS(on)3
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Total Gate Charge
Gate to Source Charge
Gate to Drain Charge
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
Q
G
Q
GS
Q
GD
V
F(S-D)
t
rr
Q
rr
TEST CONDITIONS
V
DS
= –20 V, V
GS
= 0 V
V
GS
=
!
20 V, V
DS
= 0 V
V
DS
= –10 V, I
D
= –1 mA
V
DS
= –10 V, I
D
= –1.5 A
V
GS
= –10 V, I
D
= –1.5 A
V
GS
= –4.5 V, I
D
= –1.5 A
V
GS
= –4.0 V, I
D
= –1.5 A
V
DS
= –10 V
V
GS
= 0 V
f = 1 MHz
V
DD
= –10 V
I
D
= –2.0 A
V
GS(on)
= –4.0 V
R
G
= 10
Ω
V
DD
= –10 V
I
D
= –2.5 A
V
GS
= –4.0 V
I
F
= 2.5 A, V
GS
= 0 V
I
F
= 2.5 A, V
GS
= 0 V
di/dt = 20 A /
µ
s
–1.0
1
–1.5
3.5
83
141
163
220
240
50
110
500
160
310
8.3
2.4
4.7
0.82
40
6.5
105
210
250
MIN.
TYP.
MAX.
–10
!
10
UNIT
µ
A
µ
A
V
S
mΩ
mΩ
mΩ
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
ns
nC
–2.5
5
TEST CIRCUIT 1 SWITCHING TIME
TEST CIRCUIT 2 GATE CHARGE
D.U.T.
D.U.T.
R
L
PG.
R
G
V
DD
I
D
(−)
V
GS
(−)
0
τ
τ
= 1
µ
s
Duty Cycle
≤
1 %
I
D
Wave Form
V
GS
(−)
V
GS
Wave Form
I
G
=
−2
mA
V
GS
(on)
90 %
R
L
V
DD
0
10 %
PG.
90 %
90 %
50
Ω
I
D
0 10 %
10 %
t
d(on)
t
on
t
r
t
d(off)
t
off
t
f
2
Data Sheet D12733EJ2V0DS00
µ
PA1851
5
TYPICAL CHARACTERISTICS (T
A
= 25°C)
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
100
80
FORWARD BIAS SAFE OPERATING AREA
−100
dT - Derating Factor - %
I
D
- Drain Current - A
−10
)
L
−
10
on
=
S(
R
D GS
d
ite V)
im
I
D (pulse)
PW
60
V
(@
I
D (DC)
10
ms
10
0m
s
DC
=1
ms
−1
40
−0.1
20
0
30
60
90
120
150
−0.01
−0.1
Single Pulse
Mounted on Ceramic
2
Substrate of 50 cm x 1.1 mm
P
D
(FET1) : P
D
(FET2) = 1:1
−1
−10
−100
T
A
- Ambient Temperature -
˚C
V
DS
- Drain to Source Voltage - V
−12
−10
DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE
V
GS
=
−10
V
TRANSFER CHARACTERISTICS
−100
−10
I
D
- Drain Current - A
V
DS
=
−10
V
I
D
- Drain Current - A
−8
−6
−4
−2
0
0
−4.5
V
−1
−0.1
−0.01
−0.001
T
A
= 125˚C
75˚C
25˚C
−25˚C
−1
−4
−
4.0 V
−0.0001
−0.2
−0.4
−0.6
−0.8
−1.0
−0.00001
0
−2
−3
−5
−6
V
DS
- Drain to Source Voltage - V
V
GS
- Gate to Source Voltage - V
V
GS(off)
- Gate to Source Cut-off Voltage - V
−2.0
GATE TO SOURCE CUT-OFF VOLTAGE vs.
CHANNEL TEMPERATURE
FORWARD TRANSFER ADMMITTANCE Vs.
DRAIN CURRENT
100
−1.5
| y
fs
| - Forward Transfer Admittance - S
V
DS
=
−10
V
I
D
=
−1
mA
V
DS
=
−10
V
10
T
A
=
−25
˚C
25
˚C
75
˚C
125
˚C
−1.0
1
−0.5
−50
0
50
100
150
T
ch
- Channel Temperature - ˚C
0.1
−0.1
−1
−10
−100
I
D
- Drain Current - A
Data Sheet D12733EJ2V0DS00
3
µ
PA1851
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
DRAIN CURRENT
400
V
GS
=
−4.0
V
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
DRAIN CURRENT
400
V
GS
=
−4.5
V
300
R
DS(on)
- Drain to Source On-State Resistance - mΩ
300
T
A
= 125˚C
200
75˚C
25˚C
−25˚C
R
DS(on)
- Drain to Source On-State Resistance - mΩ
200
T
A
= 125˚C
75˚C
25˚C
−25˚C
100
100
0
−
0.1
−
1
−
10
0
−
0.1
−
1
−
10
−
100
I
D
- Drain Current - A
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
DRAIN CURRENT
200
V
GS
=
−10
V
160
I
D
- Drain Current - A
R
DS(on)
- Drain to Source On-State Resistance - mΩ
R
DS (on)
- Drain to Source On-state Resistance - mΩ
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CHANNEL TEMPERATURE
300
I
D
=
−1.5
A
200
V
GS
=
−4.0
V
−4.5
V
120
T
A
= 125˚C
75˚C
25˚C
−25˚C
80
100
−10
V
40
0
−
0.1
−
1
−
10
−
100
0
−50
I
D
- Drain Current - A
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE
300
250
200
150
100
50
0
0
50
100
T
ch
- Channel Temperature - ˚C
CAPACITANCE vs. DRAIN TO
SOURCE VOLTAGE
150
R
DS (on)
- Drain to Source On-state Resistance - mΩ
1000
C
iss
, C
oss
, C
rss
- Capacitance - pF
I
D
=
−1.5
A
f = 1 MHz
C
iss
C
oss
100
C
rss
0
−
4
−
8
10
−1
−10
V
DS
- Drain to Source Voltage - V
−100
−
12
−
16
−
20
V
GS
- Gate to Source Voltage - V
4
Data Sheet D12733EJ2V0DS00
µ
PA1851
SWITCHING CHARACTERISTICS
1000
t
d(on)
, t
r
, t
d(off)
, t
f
- Swwitchig Time - ns
SOURCE TO DRAIN DIODE FORWARD VOLTAGE
10
V
GS
= 0 V
I
F
- Source to Drain Current - A
t
r
t
f
t
d(on)
t
d(off)
1
0.1
100
0.01
10
−0.1
V
DD
=
−10
V
V
GS(on)
=
−4.0
V
R
G
= 10
Ω
−1
I
D
- Drain Current - A
−10
0.001
0.0001
0.4
0.6
0.8
1
V
F(S-D)
- Source to Drain Voltage - V
1.2
DYNAMIC INPUT CHARACTERISTICS
8
I
D
=
−2.5
A
V
DD
=
−4.0
V
6
V
DD
=
−10
V
V
DD
=
−16
V
4
V
GS
- Gate to Source Voltage - V
2
0
0
3
6
9
12
15
Q
G
- Gate Charge - nC
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
1000
r
th(t)
- Transient Thermal Resistance - ˚C/W
100
62.5
˚C/W
10
1
Mounted on Ceramic Substrate
of 50cm
2
x 1.1 mm
Single Pulse
P
D
(FET1) : P
D
(FET2) = 1:1
0.1
1m
10 m
100 m
1
PW - Pulse Width - s
10
100
1000
Data Sheet D12733EJ2V0DS00
5
京公网安备 11010802033920号
EEWORLD
