UPD44165364F5-E40-EQ1 datasheet, PDF

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UPD44165364F5-E40-EQ1: DescriptionQDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, PLASTIC, FBGA-165; Categorystorage storage; File Size269KB，32 Pages; ManufacturerNEC Electronics

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UPD44165364F5-E40-EQ1 Overview

QDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, PLASTIC, FBGA-165

UPD44165364F5-E40-EQ1 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	NEC Electronics
package instruction	13 X 15 MM, PLASTIC, FBGA-165
Reach Compliance Code	compliant
Maximum access time	0.45 ns
JESD-30 code	R-PBGA-B165
JESD-609 code	e0
length	15 mm
memory density	18874368 bit
Memory IC Type	QDR SRAM
memory width	36
Number of functions	1
Number of terminals	165
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	512KX36
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	13 mm

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PRELIMINARY DATA SHEET

MOS INTEGRATED CIRCUIT

PD44165084, 44165184, 44165364

18M-BIT QDR

II SRAM

4-WORD BURST OPERATION

Description

The

PD44165084 is a 2,097,152-word by 8-bit, the

PD44165184 is a 1,048,576-word by 18-bit and the

PD44165364 is a 524,288-word by 36-bit synchronous quad data rate static RAM fabricated with advanced CMOS

technology using full CMOS six-transistor memory cell.

The

PD44165084,

PD44165184 and

PD44165364 integrates unique synchronous peripheral circuitry and a

burst counter. All input registers controlled by an input clock pair (K and /K) are latched on the positive edge of K and

/K.

These products are suitable for application which require synchronous operation, high speed, low voltage, high

density and wide bit configuration.

These products are packaged in 165-pin PLASTIC FBGA.

Features

•

1.8 ± 0.1 V power supply and HSTL I/O

•

DLL circuitry for wide output data valid window and future frequency scaling

•

Separate independent read and write data ports with concurrent transactions

•

100% bus utilization DDR READ and WRITE operation

•

Four-tick burst for reduced address frequency

•

Two input clocks (K and /K) for precise DDR timing at clock rising edges only

•

Two output clocks (C and /C) for precise flight time

and clock skew matching-clock and data delivered together to receiving device

•

Internally self-timed write control

•

Clock-stop capability with

s restart

•

User programmable impedance output

•

Fast clock cycle time : 4.0 ns (250 MHz) , 5.0 ns (200 MHz) , 6.0 ns (167 MHz)

•

Simple control logic for easy depth expansion

•

JTAG boundary scan

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for

availability and additional information.

Document No. M15825EJ4V0DS00 (4th edition)

Date Published June 2003 NS CP(K)

Printed in Japan

The mark

shows major revised points.

2001

UPD44165364F5-E40-EQ1 Related Products

	UPD44165364F5-E40-EQ1	UPD44165364F5-E40-EQ1-A
Description	QDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, PLASTIC, FBGA-165	QDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, PLASTIC, FBGA-165
Is it Rohs certified?	incompatible	conform to
package instruction	13 X 15 MM, PLASTIC, FBGA-165	13 X 15 MM, PLASTIC, FBGA-165
Reach Compliance Code	compliant	compliant
Maximum access time	0.45 ns	0.45 ns
JESD-30 code	R-PBGA-B165	R-PBGA-B165
JESD-609 code	e0	e1
length	15 mm	15 mm
memory density	18874368 bit	18874368 bit
Memory IC Type	QDR SRAM	QDR SRAM
memory width	36	36
Number of functions	1	1
Number of terminals	165	165
word count	524288 words	524288 words
character code	512000	512000
Operating mode	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C
organize	512KX36	512KX36
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	BGA	BGA
Package shape	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY	GRID ARRAY
Parallel/Serial	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED
Certification status	Not Qualified	Not Qualified
Maximum supply voltage (Vsup)	1.9 V	1.9 V
Minimum supply voltage (Vsup)	1.7 V	1.7 V
Nominal supply voltage (Vsup)	1.8 V	1.8 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL
Terminal surface	TIN LEAD	TIN SILVER COPPER
Terminal form	BALL	BALL
Terminal pitch	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED
width	13 mm	13 mm

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Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

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