EEWORLDEEWORLDEEWORLD

Part Number

Search

530EB301M000DG

Description
LVPECL Output Clock Oscillator, 301MHz Nom, ROHS COMPLIANT, SMD, 6 PIN
CategoryPassive components    oscillator   
File Size215KB,12 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance  
Download Datasheet Parametric View All

530EB301M000DG Overview

LVPECL Output Clock Oscillator, 301MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

530EB301M000DG Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerSilicon Laboratories Inc
package instructionROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Codeunknown
Other featuresTRAY
maximum descent time0.35 ns
Frequency Adjustment - MechanicalNO
frequency stability20%
JESD-609 codee4
Manufacturer's serial number530
Installation featuresSURFACE MOUNT
Nominal operating frequency301 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeLVPECL
physical size7.0mm x 5.0mm x 1.85mm
longest rise time0.35 ns
Maximum supply voltage2.75 V
Minimum supply voltage2.25 V
Nominal supply voltage2.5 V
surface mountYES
maximum symmetry55/45 %
Terminal surfaceNickel/Gold (Ni/Au)
S i 5 3 0 / 5 31
R
EVISION
D
C
R Y S TA L
O
S C I L L A T O R
(XO)
(10 M H
Z T O
1.4 G H
Z
)
Features
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Ordering Information:
See page 7.
Applications
SONET/SDH
Networking
SD/HD video
Test and measurement
Clock and data recovery
FPGA/ASIC clock generation
Pin Assignments:
See page 6.
(Top View)
NC
OE
GND
1
2
3
6
5
4
V
DD
Description
The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry
to provide a low jitter clock at high frequencies. The Si530/531 is available
with any-rate output frequency from 10 to 945 MHz and select frequencies to
1400 MHz. Unlike a traditional XO, where a different crystal is required for
each output frequency, the Si530/531 uses one fixed crystal to provide a
wide range of output frequencies. This IC based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In addition,
DSPLL clock synthesis provides superior supply noise rejection, simplifying
the task of generating low jitter clocks in noisy environments typically found in
communication systems. The Si530/531 IC based XO is factory configurable
for a wide variety of user specifications including frequency, supply voltage,
output format, and temperature stability. Specific configurations are factory
programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
®
CLK–
CLK+
Si530 (LVDS/LVPECL/CML)
OE
NC
GND
1
2
3
6
5
4
V
DD
Functional Block Diagram
V
DD
CLK– CLK+
NC
CLK
Si530 (CMOS)
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL
®
Clock
Synthesis
OE
NC
GND
1
2
3
6
5
4
V
DD
CLK–
CLK+
Si531 (LVDS/LVPECL/CML)
OE
GND
Rev. 1.1 6/07
Copyright © 2007 by Silicon Laboratories
Si530/531
Maybe it's destiny?
Last year, I spent eight months preparing for the postgraduate entrance examination. I originally wanted to apply to South China University of Technology. Why did I choose this university? Because it ...
张无忌1987 Talking
The logic gates occupied by dspbuilder are compared with those occupied by VHDL to complete the same function directly.
Which one has more logic gates, the one occupied by DSPBuilder or the one occupied by VHDL to complete the same function? How much more logic gates? Today I used DSP Builder to make a keyboard debounc...
eeleader FPGA/CPLD
Programming help ahhhhhhhhhhhh
The intention of this program is to implement a function that expands 6 interrupts. Each interrupt will output serially. For example, the first interrupt outputs 001, the second outputs 010, and so on...
eeleader FPGA/CPLD
In WM6.0, there is a problem with EDB database comparison records. Experts, please help me. It's urgent!
I want to compare two records in EDB database, but I can't think of a good method. Is there any expert who knows? Please tell me. The method I can think of now is to use CeSeekDatabase, but when I use...
baiyang8361 Embedded System
Please ask about PWM question! Please help experts!
//ADC part ADC10CTL0 = ADC10SHT_2 + ADC10ON + ADC10IE+MSC; ADC10CTL1 = INCH_4+CONSEQ_2; ADC10DTC1 = Samples; ADC10AE0 |= BIT4; //PWM part TACTL = TASSEL_2 + MC_1; P1DIR |= BIT5+BIT6; P1OUT = 0; CCR0 =...
jhihj1123 Microcontroller MCU
Implementation of Automobile Instrument Software Based on CAN Bus
With more and more electronic devices in cars, car networks have emerged, and controller area networks (CAN) have begun to be widely used in cars. How to use the information in the car network to faci...
frozenviolet Automotive Electronics

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2919  1610  2840  1428  2894  59  33  58  29  11 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号