EEWORLDEEWORLDEEWORLD

Part Number

Search

HC49-3H/2C4JF20.2752MHZ

Description
Parallel - Fundamental Quartz Crystal, 20.2752MHz Nom,
CategoryPassive components    Crystal/resonator   
File Size47KB,1 Pages
ManufacturerGolledge Electronics
Websitehttp://www.golledge.com/
Environmental Compliance  
Download Datasheet Parametric View All

HC49-3H/2C4JF20.2752MHZ Overview

Parallel - Fundamental Quartz Crystal, 20.2752MHz Nom,

HC49-3H/2C4JF20.2752MHZ Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerGolledge Electronics
Reach Compliance Codecompliant
Other featuresTAPE AND REEL
Ageing3 PPM/FIRST YEAR
Crystal/Resonator TypePARALLEL - FUNDAMENTAL
Drive level100 µW
frequency stability0.01%
frequency tolerance20 ppm
load capacitance30 pF
Manufacturer's serial numberHC49-3H
Installation featuresTHROUGH HOLE MOUNT
Nominal operating frequency20.2752 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
physical sizeL11.05XB4.65XH2.5 (mm)/L0.435XB0.183XH0.098 (inch)
Series resistance50 Ω
surface mountNO
Low Profile Crystal
HC49-4H & HC49-3H
Specifications
HC49-4H: 3.5mm maximum height
HC49-3H: 2.5mm maximum height
Parameters
Package:
2.50
(max)
0.43Ø
12.00
(min)
12.00
(min)
Product
HC49-4H
HC49-3H
Option
Code
HC49-4H
HC49-3H
3.50*
(max)
0.43Ø
Frequency range:
1.0MHz
3.2768 ~ 90.0MHz
3.579 ~ 90.0MHz
Calibration tolerance:
±20ppm
±30ppm
±50ppm
Other values (±10ppm ~ ±100ppm)
±30ppm
±50ppm
±100ppm
Other values (±10ppm ~ ±100ppm)
2
3
5
specify
3
5
C
specify
1
2
3
4
specify
B
D
E
F
J
specify
F
3
4.88
4.65
11.05
4.88
4.65
11.05
Temperature stability:
HC49-4H
*1.0MHz HC49-4H height is 4.00 (max)
HC49-3H
Scale 1:1
Features
«
«
«
«
Industry standard HC49 footprint
Fundamental mode available up to 50.0MHz
Comprehensive stock of standard frequencies
Low profile for close board stacking
Operating temperature range:
-10 to +60°C
-20 to +70°C
-30 to +80°C
-40 to +85°C
Other values
Circuit condition:
12pF
16pF
18pF
20pF
30pF
Other values
Fundamental
3rd overtone
Oscillation mode:
Equivalent series resistance (max):
3000 (1.0MHz)
200 (>3.2 ~ 3.5MHz)
150 (>3.5 ~ 4.0MHz)
120 (>4.0 ~ 4.4MHz)
100 (>4.4 ~ 7.0MHz)
70 (>7.0 ~ 10.0MHz)
50 (>10.0 ~ 50.0MHz, fund)
100 (>25.0 ~ 90.0MHz, 3rd OT)
Static capacitance (C
0
):
Ageing:
7pF max
±3ppm max first year
100µW
Test drive level:
Standard.
Optional - Please specify required code(s) when ordering
Ordering Information
Product name + frequency + specification code
eg:
HC49-4H/351DF 18.4320MHz
30/50/10/16-F
HC49-3H/232S3 48.0MHz
20/30/20/S-3
Insulating washers and mounting clips available. See our website
for details.
Available on T&R - 1k pcs per reel.
Centre ground lead available on request.
Refer to our website for T&R and soldering details.
IMPORTANT: Not normally available in small quantities of
non-standard frequencies. Please check with us before ordering.
Tel:
+44 1460 256 100
03 Oct 2011
Fax:
+44 1460 256 101
E-mail:
sales@golledge.com
Web:
www.golledge.com
Upgrading bootloader failed, check the short-circuit interfaces and study again
Continuing from the previous post, KW41Z's Best Partner - [NXP Kinetis MCU] - Electronic Engineering World Forum [url]https://bbs.eeworld.com.cn/thread-529560-1-1.html[/url] According to Freescale's u...
suoma NXP MCU
Can I add components to the vxsim simulation environment? How to configure vxworks
How to include INCLUDE_POSIX_SCHED when using POSIX functions in vxsim simulation environment? If the project (downloadable) is not selected, can the project not select component configuration? Is the...
taoym101 Real-time operating system RTOS
How to understand "everything is a file"? Answer from the perspective of the application layer and the driver layer.
Dear experts, how do you understand "everything is a file"? Please answer from the perspective of the application layer and the driver layer....
zhengjiewen Linux and Android
[Design Tools] This document introduces the FPGA operation steps for a certain function using ISE10.1
The document introduces the steps of using ISE10.1 to perform FPGA operations for a certain function, including the steps of creating a new document, synthesis, functional simulation, compilation and ...
GONGHCU FPGA/CPLD
The LPC2138 P1 port connected to the 1602 LCD simulation in Pretous cannot display! !
I am building a virtual simulation platform in Proteus. When using LM1602, the sent data cannot be displayed normally. I have successfully used the same code in the P0 port of LPC2106. Because there a...
chengchuanqing Embedded System
After the layer is locked, Blt returns DDERR_SURFACEBUSY. Who returns it?
Is there any lock when executing Blt? If yes, where is it added? There is no lock in HalBlt. When the layer is locked, the Blt operation directly returns DDERR_SURFACEBUSY without entering HalBlt oper...
friday505 Embedded System

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2338  275  1893  2903  1396  48  6  39  59  29 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号