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5962-9318710HTC

Description
Cache SRAM Module, 128KX32, 17ns, CMOS, HEX-IN-LINE, SINGLE CAVITY, WITH STANDOFFS-66
Categorystorage    storage   
File Size213KB,32 Pages
ManufacturerWhite Microelectronics
Download Datasheet Parametric View All

5962-9318710HTC Overview

Cache SRAM Module, 128KX32, 17ns, CMOS, HEX-IN-LINE, SINGLE CAVITY, WITH STANDOFFS-66

5962-9318710HTC Parametric

Parameter NameAttribute value
MakerWhite Microelectronics
package instructionHEX-IN-LINE, SINGLE CAVITY, WITH STANDOFFS-66
Reach Compliance Codeunknown
Maximum access time17 ns
Other featuresCONFIGURABLE AS 512K X 8
Spare memory width16
JESD-30 codeS-XHIP-P66
JESD-609 codee4
length30.1 mm
memory density4194304 bit
Memory IC TypeCACHE SRAM MODULE
memory width32
Number of functions1
Number of terminals66
word count131072 words
character code128000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize128KX32
Package body materialUNSPECIFIED
encapsulated codeHIP
Package shapeSQUARE
Package formIN-LINE
Parallel/SerialPARALLEL
Certification statusNot Qualified
Maximum seat height6.22 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal surfaceGOLD
Terminal formPIN/PEG
Terminal pitch2.54 mm
Terminal locationHEX
width30.1 mm
REVISIONS
LTR
G
H
J
DESCRIPTION
Added device type 11. Added vendor cage 0EU86 for device type 05
through 09. -sld
Figure 1; changed the maximum limit for dimension D3 from 1.060
inches to 1.086 inches for case outlines 4 and 5. -sld
Added note to paragraph 1.2.2 and table I regarding the 4 transistor
design. Added footnote 3 for case outlines U, T, X, And Y on the
bulletin page. Redrew entire document. -sld
Added device types 12 through 18. -sld
DATE (YR-MO-DA)
99-08-27
00-02-07
00-11-14
APPROVED
Raymond Monnin
Raymond Monnin
Raymond Monnin
K
01-11-13
Raymond Monnin
REV
SHEET
REV
SHEET
REV STATUS
OF SHEETS
PMIC N/A
K
15
K
16
K
17
K
18
REV
SHEET
PREPARED BY
Steve L. Duncan
CHECKED BY
Michael C. Jones
K
19
K
20
K
21
K
1
K
22
K
2
K
23
K
3
K
24
K
4
K
25
K
5
K
26
K
6
K
7
K
8
K
9
K
10
K
11
K
12
K
13
K
14
STANDARD
MICROCIRCUIT
DRAWING
THIS DRAWING IS
AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216
APPROVED BY
Kendall A. Cottongim
MICROCIRCUIT, HYBRID, DIGITAL, STATIC
RANDOM ACCESS MEMORY, CMOS, 128K x
32-BIT
SIZE
A
SHEET
CAGE CODE
DRAWING APPROVAL DATE
94-06-24
REVISION LEVEL
K
67268
1 OF
26
5962-93187
DSCC FORM 2233
APR 97
DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.
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