1M
X28LV010
3.3 Volt, Byte Alterable E
2
PROM
128K x 8 Bit
FEATURES
• Access Time: 70, 90, 120, 150ns
• Simple Byte and Page Write
—Single 3.3V±10% supply
—No external high voltages or V
PP
control circuits
—Self-timed
• no erase before write
• no complex programming algorithms
• no overerase problem
• Low Power CMOS
—Active: 20mA
—Standby: 20µA
• Software Data Protection
—Protects data against system level inadvertant
writes
• High Speed Page Write Capability
• Highly Reliable Direct Write
™
Cell
—Endurance: 100,000 write cycles
—Data retention: 100 Years
• Early End of Write Detection
—DATA polling
—Toggle bit polling
BLOCK DIAGRAM
DESCRIPTION
The Xicor X28LV010 is a 128K x 8 E
2
PROM, fabri-
cated with Xicor's proprietary, high performance, float-
ing gate CMOS technology. Like all Xicor
programmable non-volatile memories the X28LV010
requires a single voltage supply. The X28LV010 fea-
tures the JEDEC approved pinout for byte-wide memo-
ries, compatible with industry standard EPROMs.
The X28LV010 supports a 256-byte page write opera-
tion, effectively providing a 12µs/byte write cycle and
enabling the entire memory to be typically written in
less than 2.5 seconds. The X28LV010 also features
DATA Polling and Toggle Bit Polling, system software
support schemes used to indicate the early completion
of a write cycle. In addition, the X28LV010 supports
Software Data Protection option.
Xicor E
2
PROMs are designed and tested for applica-
tions requiring extended endurance. Data retention is
specified to be greater than 100 years.
A
8
–A
16
X Buffers
Latches and
Decoder
1M-Bit
E
2
PROM
Array
A
0
–A
7
Y Buffers
Latches and
Decoder
I/O Buffers
and Latches
I/O
0
–I/O
7
Data Inputs/Outputs
CE
OE
WE
V
CC
V
SS
Control
Logic and
Timing
Xicor, Inc. 2000 Patents Pending
2000-4003 9/6/00 EP
Characteristics subject to change without notice.
1 of 18
X28LV010
PIN CONFIGURATIONS
PDIP
X28LV010
NC
A
16
A
15
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
WE
NC
A
14
A
13
A
8
A
9
A
11
OE
A
10
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
PLCC
NC
V
CC
A
12
A
15
A
16
WE
NC
TSOP
X28LV010
A
11
A
9
A
8
A
13
A
14
NC
NC
NC
WE
V
CC
NC
NC
NC
A
16
A
15
A
12
A
7
A
6
A
5
A
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
OE
A
10
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
NC
NC
V
SS
NC
NC
I/O
2
I/O
1
I/O
0
A
0
A
1
A
2
A
3
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
54
6
7
8
9
10
11
CE
12
13
15 16 17 18 1920 21 I/O
7
14
I/O
1
I/O
2
V
SS
I/O
3
I/O
4
I/O
5
I/O
6
30
3 2
32 31
29
1
28
27
26
X28LV010
25
(Top View)
24
23
22
A
14
A
13
A
8
A
9
A
11
OE
A
10
PIN DESCRIPTIONS
Addresses (A
0
–A
16
)
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all
read/write operations. When CE is HIGH, power con-
sumption is reduced.
Output Enable (OE)
The Output Enable input controls the data output buff-
ers and is used to initiate read operations.
Data In/Data Out (I/O
0
–I/O
7
)
Data is written to or read from the X28LV010 through
the I/O pins.
Write Enable (WE)
The Write Enable input controls the writing of data to
the X28LV010.
PIN NAMES
Symbol
A
0
–A
16
I/O
0
–I/O
7
WE
CE
OE
V
CC
V
SS
NC
Description
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
+3.3V
Ground
No Connect
DEVICE OPERATION
Read
Read operations are initiated by both OE and CE
LOW. The read operation is terminated by either CE or
OE returning HIGH. This two line control architecture
eliminates bus contention in a system environment.
The data bus will be in a high impedance state when
either OE or CE is HIGH.
Characteristics subject to change without notice.
2 of 18
X28LV010
Write
Write operations are initiated when both CE and WE
are LOW and OE is HIGH. The X28LV010 supports
both a CE and WE controlled write cycle. That is, the
address is latched by the falling edge of either CE or
WE, whichever occurs last. Similarly, the data is
latched internally by the rising edge of either CE or
WE, whichever occurs first. A byte write operation,
once initiated, will automatically continue to comple-
tion, typically within 5ms.
Page Write Operation
The page write feature of the X28LV010 allows the
entire memory to be written in 2.5 seconds. Page write
allows two to two hundred fifty-six bytes of data to be
consecutively written to the X28LV010 prior to the
commencement of the internal programming cycle.
The host can fetch data from another device within the
system during a page write operation (change the
source address), but the page address (A
8
through
A
16
) for each subsequent valid write cycle to the part
during this operation must be the same as the initial
page address.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host
can write an additional one to two hundred fifty five
bytes in the same manner as the first byte was written.
Each successive byte load cycle, started by the WE
HIGH to LOW transition, must begin within 100µs of
the falling edge of the preceding WE. If a subsequent
WE HIGH to LOW transition is not detected within
100µs, the internal automatic programming cycle will
commence. There is no page write window limitation.
Effectively the page write window is infinitely wide, so
long as the host continues to access the device within
the byte load cycle time of 100µs.
Write Operation Status Bits
The X28LV010 provides the user two write operation
status bits. These can be used to optimize a system
write cycle time. The status bits are mapped onto the
I/O bus as shown in Figure 1.
Figure 1. Status Bit Assignment
I/O
DP
TB
5
4
3
2
1
0
Reserved
Toggle Bit
DATA Polling
DATA Polling (I/O
7
)
The X28LV010 features DATA Polling as a method to
indicate to the host system that the byte write or page
write cycle has completed. DATA Polling allows a sim-
ple bit test operation to determine the status of the
X28LV010, eliminating additional interrupt inputs or
external hardware. During the internal programming
cycle, any attempt to read the last byte written will pro-
duce the complement of that data on I/O
7
(i.e., write
data = 0xxx xxxx, read data = 1xxx xxxx). Once the
programming cycle is complete, I/O
7
will reflect true
data. Note: If the X28LV010 is in the protected state
and an illegal write operation is attempted DATA Polling
will not operate.
Toggle Bit (I/O
6
)
The X28LV010 also provides another method for deter-
mining when the internal write cycle is complete. Dur-
ing the internal programming cycle, I/O
6
will toggle
from HIGH to LOW and LOW to HIGH on subsequent
attempts to read the device. When the internal cycle is
complete the toggling will cease and the device will be
accessible for additional read or write operations.
Characteristics subject to change without notice.
3 of 18
X28LV010
DATA Polling I/O
7
Figure 2. DATA Polling Bus Sequence
Last
Write
WE
CE
OE
V
IH
I/O
7
High Z
V
OL
A
0
–A
14
An
An
An
An
An
An
An
V
OH
X28LV010
Ready
Figure 3. DATA Polling Software Flow
Write Data
DATA Polling can effectively halve the time for writing to
the X28LV010. The timing diagram in Figure 2 illus-
trates the sequence of events on the bus. The software
flow diagram in Figure 3 illustrates one method of
implement-ing the routine.
Writes
Complete?
YES
Save Last Data
and Address
NO
Read Last
Address
IO
7
Compare?
YES
X28LV010
Ready
NO
Characteristics subject to change without notice.
4 of 18
X28LV010
The Toggle Bit I/O
6
Figure 4. Toggle Bit Bus Sequence
WE
Last
Write
CE
OE
V
OH
V
OL
I/O
6
High Z
X28LV010
Ready
Figure 5. Toggle Bit Software Flow
Last Write
prised of multiple X28LV010 memories that is fre-
quently updated. Toggle Bit Polling can also provide a
method for status checking in multiprocessor applica-
tions. The timing diagram in Figure 4 illustrates the
sequence of events on the bus. The software flow dia-
gram in Figure 5 illustrates a method for polling the
Toggle Bit.
HARDWARE DATA PROTECTION
The X28LV010 provides three hardware features that
protect nonvolatile data from inadvertent writes.
– Noise Protection—A WE pulse less than 10ns will
not initiate a write cycle.
– Default V
CC
Sense—All functions are inhibited when
V
CC
is
≤
2.5V.
– Write inhibit—Holding either OE LOW, WE HIGH, or
CE HIGH will prevent an inadvertent write cycle dur-
ing power-up and power-down, maintaining data
integrity.
SOFTWARE DATA PROTECTION
The X28LV010 offers a software controlled data pro-
tection feature. The X28LV010 is shipped from Xicor
with the software data protection NOT ENABLED: that
is the device will be in the standard operating mode. In
this mode data should be protected during power-up/
-down operations through the use of external circuits.
The host would then have open read and write access
of the device once V
CC
was stable.
Load ACCUM
from ADDR n
Compare
ACCUM with
ADDR n
Compare
OK?
YES
NO
Ready
The Toggle Bit can eliminate the software housekeep-
ing chore of saving and fetching the last address and
data written to a device in order to implement DATA
Polling. This can be especially helpful in an array com-
Characteristics subject to change without notice.
5 of 18
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