0.16µm Process
ADVANCE
‡
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
18Mb
SYNCBURST
™
SRAM
FEATURES
• Fast clock and OE# access times
• Single +3.3V ±0.165V or +2.5V ±0.125V power supply
(V
DD
)
• Separate +3.3V or +2.5V isolated output buffer
supply (V
DD
Q)
• SNOOZE MODE for reduced-power standby
• Common data inputs and data outputs
• Individual byte Write control and GLOBAL WRITE
• Three chip enables for simple depth expansion and
address pipelining
• Clock-controlled and registered addresses, data
I/Os, and control signals
• Internally self-timed write cycle
• Automatic power-down
• Burst control (interleaved or linear burst)
• Low capacitive bus loading
• x18, x32, and x36 versions available
MT58L1MY18D, MT58V1MV18D,
MT58L512Y32D, MT58V512V32D,
MT58L512Y36D, MT58V512V36D
3.3V V
DD
, 3.3V or 2.5V I/O; 2.5V V
DD
, 2.5V I/O
100-Pin TQFP
1
165-Ball FBGA
2
OPTIONS
• Timing (Access/Cycle/MHz)
3.1ns/5ns/200 MHz
3.5ns/6ns/166 MHz
4.2ns/7.5ns/133 MHz
5ns/10ns/100 MHz
• Configurations
3.3V V
DD
, 3.3V or 2.5V I/O
1 Meg x 18
512K x 32
512K x 36
2.5V V
DD
, 2.5V I/O
1 Meg x 18
512K x 32
512K x 36
• Packages
100-pin TQFP (3-chip enable)
165-ball FBGA
• Operating Temperature Range
Commercial (+10ºC
≤
T
J
≤
+110ºC)
Part Number Example:
TQFP
MARKING
-5
-6
-7.5
-10
1.
JEDEC-Standard MS-026 BHA (LQFP)
2. JEDEC Standard MS-216 (Var. CAB-1)
MT58L1MY18D
MT58L512Y32D
MT58L512Y36D
MT58V1MV18D
MT58V512V32D
MT58V512V36D
T
F*
None
MT58L512Y36DT-10
*A Part Marking Guide for the FBGA devices can be found on
Micron’s Web site—http://www.micron.com/numberguide.
18Mb: 1 Meg x 18, 512K x 32/36, Pipleined, DCD SyncBurst SRAM
MT58L1MY18D_16_A.fm - Rev.A; Pub 6/02
The Micron
®
SyncBurst
™
SRAM family employs
high-speed, low-power CMOS designs that are fabri-
cated using an advanced CMOS process.
Micron’s 18Mb SyncBurst SRAMs integrate a 1 Meg x
18, 512K x 32, or 512K x 36 SRAM core with advanced
synchronous peripheral circuitry and a 2-bit burst
counter. All synchronous inputs pass through registers
controlled by a positive-edge-triggered single-clock
input (CLK). The synchronous inputs include all
addresses, all data inputs, active LOW chip enable
(CE#), two additional chip enables for easy depth
expansion (CE2, CE2#), burst control inputs (ADSC#,
ADSP#, ADV#), byte write enables (BWx#), and global
write (GW#).
GENERAL DESCRIPTION
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
‡
PRODUCTS
AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.
0.16µm Process
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
Asynchronous inputs include the output enable
(OE#), clock (CLK) and snooze enable (ZZ). There is
also a burst mode input (MODE) that selects between
interleaved and linear burst modes. The data-out (Q),
enabled by OE#, is also asynchronous. WRITE cycles
can be from one to two bytes wide (x18) or from one to
four bytes wide (x32/x36), as controlled by the write
control inputs.
Burst operation can be initiated with either address
status processor (ADSP#) or address status controller
(ADSC#) inputs. Subsequent burst addresses can be
internally generated as controlled by the burst
advance input (ADV#).
Address and write control are registered on-chip to
simplify WRITE cycles. This allows self-timed write
cycles. Individual byte enables allow individual bytes
to be written. During WRITE cycles on the x18 device,
BWa# controls DQa pins/balls and DQPa; BWb# con-
trols DQb pins/balls and DQPb. During WRITE cycles
on the x32 and x36 devices, BWa# controls DQa pins/
balls and DQPa; BWb# controls DQb pins/balls and
DQPb; BWc# controls DQc pins/balls and DQPc; BWd#
controls DQd pins/balls and DQPd. GW# LOW causes
all bytes to be written. Parity bits are only available on
the x18 and x36 versions.
This device incorporates an additional pipelined
enable register which delays turning off the output
buffer an additional cycle when a deselect is executed.
This feature allows depth expansion without penaliz-
ing system performance.
The device is ideally suited for Pentium
®
and
PowerPC pipelined systems and systems that benefit
from a very wide, high-speed data bus. The device is
also ideal in generic 16-, 18-, 32-, 36-, 64-, and 72-bit-
wide applications.
Please refer to Micron’s Web site (www.micron.com/
sramds)
for the latest data sheet.
DUAL VOLTAGE I/O
The 3.3V V
DD
device is tested for 3.3V and 2.5V I/O
function. The 2.5V V
DD
device is tested for only 2.5V
I/O function.
FUNCTIONAL BLOCK DIAGRAM
1 MEG x 18
20
SA0, SA1, SAs
MODE
ADV#
CLK
ADDRESS
REGISTER
20
18
20
2
SA0-SA1
SA1'
BINARY Q1
COUNTER AND
LOGIC
CLR
Q0
SA0'
ADSC#
ADSP#
BYTE “b”
WRITE REGISTER
9
BYTE “b”
WRITE DRIVER
9
1 Meg x 9 x 2
MEMORY
ARRAY
9
18
SENSE
AMPS
18
BWb#
OUTPUT
18
REGISTERS
OUTPUT
BUFFERS
E
18
BWa#
BWE#
GW#
CE#
CE2
CE2#
OE#
BYTE “a”
WRITE REGISTER
9
BYTE “a”
WRITE DRIVER
DQs
DQPa
DQPb
ENABLE
REGISTER
18
PIPELINED
ENABLE
2
INPUT
REGISTERS
Note:
Functional block diagrams illustrate simplified device operation. See truth table, pin/ball description, and timing
diagrams for detailed information.
18Mb: 1 Meg x 18, 512K x 32/36, Pipleined, DCD SyncBurst SRAM
MT58L1MY18D_16_A.fm - Rev A; Pub 6/02
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
0.16µm Process
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
FUNCTIONAL BLOCK DIAGRAM
512K x 32/36
19
SA0, SA1, SAs
ADDRESS
REGISTER
19
17
SA0-SA1
19
MODE
ADV#
CLK
Q1
SA1'
BINARY
COUNTER
SA0'
CLR
Q0
ADSC#
ADSP#
BWd#
BYTE “d”
WRITE REGISTER
BYTE “c”
WRITE REGISTER
9
BYTE “d”
WRITE DRIVER
BYTE “c”
WRITE DRIVER
BYTE “b”
WRITE DRIVER
BYTE “a”
WRITE DRIVER
9
BWc#
9
9
512K x 8 x 4
(x32)
512K x 9 x 4
(x36)
36
SENSE
AMPS
36
OUTPUT
REGISTERS
36
BWb#
BYTE “b”
WRITE REGISTER
9
9
MEMORY
ARRAY
OUTPUT
BUFFERS
E
36
DQs
DQPa
DQPb
DQPc
DQPd
BWa#
BWE#
GW#
CE#
CE2
CE2#
OE#
BYTE “a”
WRITE REGISTER
9
9
ENABLE
REGISTER
36
PIPELINED
ENABLE
4
INPUT
REGISTERS
Note:
Functional block diagrams illustrate simplified device operation. See truth table, pin/ball description, and timing
diagrams for detailed information.
18Mb: 1 Meg x 18, 512K x 32/36, Pipleined, DCD SyncBurst SRAM
MT58L1MY18D_16_A.fm - Rev A; Pub 6/02
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
0.16µm Process
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
PIN LAYOUT (Top View)
100-PIN TQFP (3-Chip Enable)
SA
NC
NC
V
DD
Q
V
SS
NC
DQPa
DQa
DQa
V
SS
V
DD
Q
DQa
DQa
V
SS
NC
V
DD
ZZ
DQa
DQa
V
DD
Q
V
SS
DQa
DQa
NC
NC
V
SS
V
DD
Q
NC
NC
NC
SA
SA
ADV#
ADSP#
ADSC#
OE# (G#)
BWE#
GW#
CLK
V
SS
V
DD
CE2#
BWa#
BWb#
NC
NC
CE2
CE#
SA
SA
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
81
49
82
48
83
47
84
46
85
45
86
44
87
43
88
42
89
41
90
40
91
39
92
38
93
37
94
36
95
35
96
34
97
33
98
32
99
31
100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
x18
SA
SA
SA
SA
SA
SA
SA
SA
SA
V
DD
V
SS
DNU
DNU
SA0
SA1
SA
SA
SA
SA
MODE
(LBO#)
SA
SA
ADV#
ADSP#
ADSC#
OE# (G#)
BWE#
GW#
CLK
V
SS
V
DD
CE2#
BWa#
BWb#
BWc#
BWd#
CE2
CE#
SA
SA
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
81
49
82
48
83
47
84
46
85
45
86
44
87
43
88
42
89
41
90
40
91
39
92
38
93
37
94
36
95
35
96
34
97
33
98
32
99
31
100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
NF/DQPb
1
DQb
DQb
V
DD
Q
V
SS
DQb
DQb
DQb
DQb
V
SS
V
DD
Q
DQb
DQb
V
SS
NC
V
DD
ZZ
DQa
DQa
V
DD
Q
V
SS
DQa
DQa
DQa
DQa
V
SS
V
DD
Q
DQa
DQa
NF/DQPa
1
NC
NC
NC
V
DD
Q
V
SS
NC
NC
DQb
DQb
V
SS
V
DD
Q
DQb
DQb
NC
V
DD
NC
V
SS
DQb
DQb
V
DD
Q
V
SS
DQb
DQb
DQPb
NC
V
SS
V
DD
Q
NC
NC
NC
x32/x36
SA
SA
SA
SA
SA
SA
SA
SA
SA
V
DD
V
SS
DNU
DNU
SA0
SA1
SA
SA
SA
SA
MODE
(LBO#)
Notes: 1.
No Function (NF) is used on the x32 version. Parity (DQPx) is used on the x36 version.
2.
Pins 39 and 38 are reserved for address expansion; 36Mb and 72Mb, respectively.
18Mb: 1 Meg x 18, 512K x 32/36, Pipleined, DCD SyncBurst SRAM
MT58L1MY18D_16_A.fm - Rev A; Pub 6/02
NF/DQPc
1
DQc
DQc
V
DD
Q
V
SS
DQc
DQc
DQc
DQc
V
SS
V
DD
Q
DQc
DQc
NC
V
DD
NC
V
SS
DQd
DQd
V
DD
Q
V
SS
DQd
DQd
DQd
DQd
V
SS
V
DD
Q
DQd
DQd
NF/DQPd
1
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
0.16µm Process
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
TQFP PIN DESCRIPTIONS
SYMBOL
SA0
SA1
SA
BWa#
BWb#
BWc#
BWd#
TYPE
Input
DESCRIPTION
Synchronous Address Inputs: These inputs are registered and must meet the setup
and hold times around the rising edge of CLK.
Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to
be written and must meet the setup and hold times around the rising edge of CLK.
A byte write enable is LOW for a WRITE cycle and HIGH for a READ cycle. For the x18
version, BWa# controls DQa pins and DQPa; BWb# controls DQb pins and DQPb. For
the x32 and x36 versions, BWa# controls DQa pins and DQPa; BWb# controls DQb
pins and DQPb; BWc# controls DQc pins and DQPc; BWd# controls DQd pins and
DQPd. Parity is only available on the x18 and x36 versions.
Byte Write Enable: This active LOW input permits BYTE WRITE operations and must
meet the setup and hold times around the rising edge of CLK.
Global Write: This active LOW input allows a full 18-, 32-, or 36-bit WRITE to occur
independent of the BWE# and BWx# lines and must meet the setup and hold times
around the rising edge of CLK.
Clock: This signal registers the address, data, chip enable, byte write enables, and
burst control inputs on its rising edge. All synchronous inputs must meet setup and
hold times around the clock’s rising edge.
Synchronous Chip Enable: This active LOW input is used to enable the device and
conditions the internal use of ADSP#. CE# is sampled only when a new external
address is loaded.
Synchronous Chip Enable: This active LOW input is used to enable the device and is
sampled only when a new external address is loaded.
Synchronous Chip Enable: This active HIGH input is used to enable the device and is
sampled only when a new external address is loaded.
Output Enable: This active LOW, asynchronous input enables the data I/O output
drivers. G# is the JEDEC-standard term for OE#.
Synchronous Address Advance: This active LOW input is used to advance the
internal burst counter, controlling burst access after the external address is loaded.
A HIGH on this pin effectively causes wait states to be generated (no address
advance). To ensure use of correct address during a WRITE cycle, ADV# must be
HIGH at the rising edge of the first clock after an ADSP# cycle is initiated.
Synchronous Address Status Processor: This active LOW input interrupts any
ongoing burst, causing a new external address to be registered. A READ is
performed using the new address, independent of the byte write enables and
ADSC#, but dependent upon CE#, CE2, and CE2#. ADSP# is ignored if CE# is HIGH.
Power-down state is entered if CE2 is LOW or CE2# is HIGH.
Synchronous Address Status Controller: This active LOW input interrupts any
ongoing burst, causing a new external address to be registered. A READ or WRITE is
performed using the new address if CE# is LOW. ADSC# is also used to place the chip
into power-down state when CE# is HIGH.
Mode: This input selects the burst sequence. A LOW on this pin selects “linear
burst.” NC or HIGH on this pin selects “interleaved burst.” Do not alter input state
while device is operating. LBO# is the JEDEC-standard term for MODE.
Input
BWE#
GW#
Input
Input
CLK
Input
CE#
Input
CE2#
CE2
OE# (G#)
ADV#
Input
Input
Input
Input
ADSP#
Input
ADSC#
Input
MODE
(LBO#)
Input
18Mb: 1 Meg x 18, 512K x 32/36, Pipleined, DCD SyncBurst SRAM
MT58L1MY18D_16_A.fm - Rev A; Pub 6/02
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
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