KMM377S1723AT3
Revision History
Revision 0.0 (June 7, 1999)
PC100 Registered DIMM
• Changed tRDL from 1CLK to 2CLK in OPERATING AC PARAMETER.
• Skip ICC4 value of CL=2 in DC characteristics in datasheet.
• Define a new parameter of tDAL( 2CLK +20ns), Last data in to Active delay in OPERATING AC PARAMETER.
• Eliminated FREQUENCY vs.PARAMETER RELATIONSHIP TABLE.
• Symbol Change Notice
I
IL
I
IL
I
OL
Before
Input leakage current (inputs)
Input leakage current (I/O pins)
Output open @ DC characteristic table
I
LI
Io
After
Input leakage current
Output open @ DC characteristic table
•
Test Condition in
DC CHARACTERISTIC Change Notice
Symbol
I
CC2P ,
I
CC3P
I
CC2N ,
I
CC3N
I
CC4
Before
CKE
≤
V
IL
(max), t
CC
= 15ns
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 15ns
Input signals are changed one time during 30ns
2 Banks activated
After
CKE
≤
V
IL
(max), t
CC
= 10ns
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
4 Banks activated
Revision 0.1 (July 5, 1999)
• Added Notes @OPERATING AC PARAMETER
Notes : 5. For -H/L, tRDL=1CLK and tDAL=1CLK+20ns is also supported .
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + 20ns.
• Redefind feedback capacitor value to Cb, variable value @ Functional Block Diagram.
Rev. 0.1 July 1999
KMM377S1723AT3
KMM377S1723AT3 SDRAM DIMM (Intel 1.2 ver Base)
PC100 Registered DIMM
16Mx72 SDRAM DIMM with PLL & Register based on 16Mx8, 4Banks 4K Ref., 3.3V Synchronous DRAMs with SPD
GENERAL DESCRIPTION
The Samsung KMM377S1723AT3 is a 16M bit x 72 Synchro-
nous Dynamic RAM high density memory module. The Sam-
sung KMM377S1723AT3 consists of nine CMOS 16Mx8 bit
Synchronous DRAMs in TSOP-II 400mil packages, two 18-bits
Drive ICs for input control signal, one PLL in 24-pin TSSOP-
package for clock and one 2K EEPROM in 8-pin TSSOP pack-
age for Serial Presence Detect on a 168pin glass-epoxy
substrate. Two 0.22uF and one 0.0022uF decoupling capaci-
tors are mounted on the printed circuit board in parallel for each
SDRAM. The KMM377S1723AT3 is a Dual In-line Memory
Module and is intented for mounting into 168-pin edge connec-
tor sockets.
Synchronous design allows precise cycle control with the use
of system clock. I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable latencies
allows the same device to be useful for a variety of high band-
width, high performance memory system applications.
FEATURE
• Performance range
Part No.
KMM377S1723AT3-GH
KMM377S1723AT3-GL
•
•
•
•
•
Max Freq. (Speed)
100MHz (10ns @ CL=2)
100MHz (10ns @ CL=3)
Burst mode operation
Auto & self refresh capability (4096 Cycles/64ms)
LVTTL compatible inputs and outputs
Single 3.3V
±
0.3V power supply
MRS cycle with address key programs
Latency (Access from column address)
Burst length (1, 2, 4, 8 & Full page)
Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the
system clock
• Serial presence detect with EEPROM
• PCB :
Height (1,500mil),
double sided component
PIN CONFIGURATIONS (Front side/back side)
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Front
V
SS
DQ0
DQ1
DQ2
DQ3
V
DD
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
V
DD
DQ14
DQ15
CB0
CB1
V
SS
NC
NC
V
DD
WE
DQM0
Pin
Front
Pin
Front
DQ18
DQ19
V
DD
DQ20
NC
*V
REF
*CKE1
V
SS
DQ21
DQ22
DQ23
V
SS
DQ24
DQ25
DQ26
DQ27
V
DD
DQ28
DQ29
DQ30
DQ31
V
SS
*CLK2
NC
WP
**SDA
**SCL
V
DD
Pin
Back
Pin
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
Back
DQM5
*CS1
RAS
V
SS
A1
A3
A5
A7
A9
BA0
A11
V
DD
*CLK1
*A12
V
SS
CKE0
*CS3
DQM6
DQM7
*A13
V
DD
NC
NC
CB6
CB7
V
SS
DQ48
DQ49
Pin
Back
29 DQM1 57
58
CS0
30
59
31
DU
60
32
V
SS
61
33
A0
62
34
A2
63
35
A4
64
36
A6
65
37
A8
38 A10/AP 66
67
39
BA1
68
40
V
DD
69
41
V
DD
42 CLK0 70
71
43
V
SS
72
44
DU
73
45
CS2
46 DQM2 74
47 DQM3 75
76
48
DU
77
49
V
DD
78
50
NC
79
51
NC
80
52
CB2
81
53
CB3
82
54
V
SS
55 DQ16 83
56 DQ17 84
V
SS
85
86 DQ32
87 DQ33
88 DQ34
89 DQ35
V
DD
90
91 DQ36
92 DQ37
93 DQ38
94 DQ39
95 DQ40
V
SS
96
97 DQ41
98 DQ42
99 DQ43
100 DQ44
101 DQ45
102 V
DD
103 DQ46
104 DQ47
105 CB4
106 CB5
V
SS
107
NC
108
NC
109
110 V
DD
111 CAS
112 DQM4
141 DQ50
142 DQ51
143 V
DD
144 DQ52
NC
145
146 *V
REF
147 REGE
V
SS
148
149 DQ53
150 DQ54
151 DQ55
V
SS
152
153 DQ56
154 DQ57
155 DQ58
156 DQ59
157 V
DD
158 DQ60
159 DQ61
160 DQ62
161 DQ63
V
SS
162
163 *CLK3
NC
164
165 **SA0
166 **SA1
167 **SA2
168 V
DD
PIN NAMES
Pin Name
A0 ~ A11
BA0 ~ BA1
DQ0 ~ DQ63
CB0 ~ CB7
CLK0
CKE0
CS0, CS2
RAS
CAS
WE
DQM0 ~ 7
V
DD
V
SS
*V
REF
REGE
SDA
SCL
SA0 ~ 2
DU
NC
WP
Function
Address input (Multiplexed)
Select bank
Data input/output
Check bit (Data-in/data-out)
Clock input
Clock enable input
Chip select input
Row address strobe
Colume address strobe
Write enable
DQM
Power supply (3.3V)
Ground
Power supply for reference
Register enable
Serial data I/O
Serial clock
Address in EEPROM
Don′t use
No connection
Write protection
* These pins are not used in this module.
**
These pins should be NC in the system
which does not support SPD.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.1 July 1999
KMM377S1723AT3
PIN CONFIGURATION DESCRIPTION
Pin
CLK
CS
Name
System clock
Chip select
PC100 Registered DIMM
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+tss prior to valid command.
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA11, Column address : CA0 ~ CA9
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
The device operates in the transparent mode when REGE is low. When REGE is high,
the device operates in the registered mode. In registered mode, the Address and con-
trol inputs are latched if CLK is held at a high or low logic level. the inputs are stored in
the latch/flip-flop on the rising edge of CLK. REGE is tied to V
DD
through 10K ohm
Resistor on PCB. So if REGE of module is floating, this module will be operated as reg-
istered mode.
Data inputs/outputs are multiplexed on the same pins.
Check bits for ECC.
WP pin is connected to V
SS
through 47KΩ Resistor.
When WP is "high", EEPROM Programming will be inhibited and the entire memory will
be write-protected.
Power and ground for the input buffers and the core logic.
CKE
Clock enable
A0 ~ A11
BA0 ~ BA1
RAS
CAS
WE
DQM0 ~ 7
Address
Bank select address
Row address strobe
Column address strobe
Write enable
Data input/output mask
REGE
Register enable
DQ0 ~ 63
CB0 ~ 7
WP
V
DD
/V
SS
Data input/output
Check bit
Write protection
Power supply/ground
Rev. 0.1 July 1999
KMM377S1723AT3
FUNCTIONAL BLOCK DIAGRAM
PCLK0
BCS0
BCKE0
B
0
A0~B
0
A11,BBA0~1,BRAS,BCAS,BWE
BDQM0
DQ0~7
10Ω
PC100 Registered DIMM
•
•
•
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
D0
•
•
DQ8~15
10Ω
PCLK1
•
D1
•
•
•
•
•
•
D2
BDQM1
CB0~7
10Ω
BCS2
•
D3
BDQM2
DQ16~23
10Ω
PCLK3
•
•
•
BDQM3
DQ24~31
10Ω
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
D4
•
BDQM4
DQ32~39
10Ω
•
D5
•
BDQM5
DQ40~47
10Ω
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
D6
•
•
•
D7
BDQM6
DQ48~55
10Ω
D8
BDQM7
DQ56~63
10Ω
Notes :
Address/Control Signals are connected to D2 through 100 ohms resistor.
A0~A9
RAS,CAS,WE
DQM0,1,4,5
CS0
REGE
PCLK2
10kΩ
Cb
*2
V
DD
SN74ALVC162835
B
0
A0~B
0
A9
BRAS,BCAS,BWE
BDQM0,1,4,5
BCS0
V
SS
V
DD
2G
AGND
1G
AVCL
CDC2509
10Ω
CLK0
12pF
LE
OE
CLK
1Y0
1Y1
1Y2
1Y3
1Y4
2Y0
2Y1
PCLK
0PCL
K1
FBOU
A10,A11,BA0~1
CS2
CKE0
DQM2,3,6,7
SN74ALVC162835
B
0
A10,B
0
A11,BBA0~1
BCS2
BCKE0
BDQM2,3,6,7
* Note
1. Unused clock termination : 10Ω and 12pF
2. The actual values of
Cb
will depend upon the PLL chosen.
Serial PD
SCL
WP
47KΩ
A0
A1
A2
SDA
LE
OE
SA0 SA1 SA2
Rev. 0.1 July 1999
KMM377S1723AT3
PC100 Registered DIMM
STANDARD TIMING DIAGRAM WITH PLL & REGISTER (CL=2, BL=4)
*2
*1
Control Signal(RAS,CAS,WE)
REG
*3
D
8
9
10
11
OUT
*1. Register Input
0
CLK
1
2
3
4
5
6
7
12
13
14
15
16
17
18
19
RAS
CAS
WE
*2. Register Output
RAS
td
tr
td
tr
CAS
WE
*3. SDRAM
CAS latency(refer to *1)
=2CLK+1CLK
tSAC
tRAC(refer to *1)
1CLK
DQ
tRAC(refer to *2)
Qa0
Qa1
Qa2
Qa3
Db0
Db1
Db2
Db3
CAS latency(refer to *2)
=2CLK
tRDL
Row Active
Read
Command
Precharge
Command
Row Active
Write
Command
Precharge
Command
td, tr = Delay of register (74ALVC162835)
Notes :
1. In case of module timing, command cycles delayed 1CLK with respect to external input timing at the address and input signal
because of the buffering in register (74ALVC162835). Therefore, Input/Output signals of read/write function should be
issued 1CLK earlier as compared to Unbuffered DIMMs.
2. D
IN
is to be issued 1clock after write command in external timing because D
IN
is issued directly to module.
: Don
′t
care
Rev. 0.1 July 1999
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