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HR1L3N-AZ

Description
1A, 60V, PNP, Si, POWER TRANSISTOR
CategoryDiscrete semiconductor    The transistor   
File Size121KB,6 Pages
ManufacturerRenesas Electronics Corporation
Websitehttps://www.renesas.com/
Download Datasheet Parametric View All

HR1L3N-AZ Overview

1A, 60V, PNP, Si, POWER TRANSISTOR

HR1L3N-AZ Parametric

Parameter NameAttribute value
MakerRenesas Electronics Corporation
Reach Compliance Codecompliant
ECCN codeEAR99
Other featuresBUILT-IN BIAS RESISTOR RATIO IS 2.12
Shell connectionCOLLECTOR
Maximum collector current (IC)1 A
Collector-emitter maximum voltage60 V
ConfigurationSINGLE WITH BUILT-IN RESISTOR
Minimum DC current gain (hFE)50
JESD-30 codeR-PSSO-F3
Number of components1
Number of terminals3
Maximum operating temperature150 °C
Package body materialPLASTIC/EPOXY
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Polarity/channel typePNP
Certification statusNot Qualified
surface mountYES
Terminal formFLAT
Terminal locationSINGLE
Maximum time at peak reflow temperatureNOT SPECIFIED
transistor applicationsSWITCHING
Transistor component materialsSILICON
DATA SHEET
COMPOUND TRANSISTOR
HR1 SERIES
on-chip resistor PNP silicon epitaxial transistor
For mid-speed switching
FEATURES
• Up to 2A high current drives such as IC outputs and actuators
available
• On-chip bias resistor
• Low power consumption during drive
PACKAGE DRAWING (UNIT: mm)
HR1 SERIES LISTS
Products
HR1A3M
HR1F3P
HR1L3N
HR1A4,
HR1L2Q
HR1F2Q
HR1A4A
Marking
MP
MQ
MR
MS
MT
MU
MX
R
1
(KΩ)
1.0
2.2
4.7
10
0.47
0.22
R
2
(KΩ)
1.0
10
10
10
4.7
2.2
10
ABSOLUTE MAXIMUM RATINGS (Ta = 25°C)
°
Parameter
Collector to base voltage
Collector to emitter voltage
Emitter to base voltage
Collector current (DC)
Collector current (Pulse)
Base current (DC)
Total power dissipation
Junction temperature
Storage temperature
Symbol
V
CBO
V
CEO
V
EBO
I
C(DC)
I
C(pulse)
*
I
B(DC)
P
T
**
T
j
T
stg
Ratings
−60
−60
−10
−1.0
−2.0
−0.02
2.0
150
−55
to +150
Unit
V
V
V
A
A
A
W
°C
°C
* PW
10 ms, duty cycle
50 %
** When 0.7 mm
×
16 cm ceramic board is used
2
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. D16184EJ2V0DS00 (2nd edition)
Date Published April 2002 N CP(K)
Printed in Japan
©
2002
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