KMM366S1723T-G8 datasheet, PDF

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KMM366S1723T-G8: DescriptionSynchronous DRAM Module, 16MX64, 6ns, CMOS, DIMM-168; Categorystorage storage; File Size149KB，11 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/

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KMM366S1723T-G8 Overview

Synchronous DRAM Module, 16MX64, 6ns, CMOS, DIMM-168

KMM366S1723T-G8 Parametric

Parameter Name	Attribute value
Maker	SAMSUNG
Objectid	1497548337
Parts packaging code	DIMM
package instruction	DIMM, DIMM168
Contacts	168
Reach Compliance Code	unknown
ECCN code	EAR99
compound_id	9464048
access mode	FOUR BANK PAGE BURST
Maximum access time	6 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	125 MHz
I/O type	COMMON
JESD-30 code	R-XDMA-N168
memory density	1073741824 bit
Memory IC Type	SYNCHRONOUS DRAM MODULE
memory width	64
Number of functions	1
Number of ports	1
Number of terminals	168
word count	16777216 words
character code	16000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	16MX64
Output characteristics	3-STATE
Package body material	UNSPECIFIED
encapsulated code	DIMM
Encapsulate equivalent code	DIMM168
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
power supply	3.3 V
Certification status	Not Qualified
refresh cycle	4096
self refresh	YES
Maximum standby current	0.008 A
Maximum slew rate	1.6 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	NO LEAD
Terminal pitch	1.27 mm
Terminal location	DUAL

KMM366S1723T-G8 Preview

KMM366S1723T

Revision History

Revision .1 (July 1998)

- Package Dimensions is revised.

Preliminary

PC100 SDRAM MODULE

REV. 1 July 1998

KMM366S1723T

KMM366S1723T SDRAM DIMM

Preliminary

PC100 SDRAM MODULE

16Mx64 SDRAM DIMM based on 16Mx8, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD

GENERAL DESCRIPTION

The Samsung KMM366S1723T is a 16M bit x 64 Synchronous

Dynamic RAM high density memory module. The Samsung

KMM366S1723T consists of eight CMOS 16M x 8 bit with

4banks Synchronous DRAMs in TSOP-II 400mil package and a

2K EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy

substrate. Two 0.1uF decoupling capacitors are mounted on the

printed circuit board in parallel for each SDRAM.

The KMM366S1723T is a Dual In-line Memory Module and is

intended for mounting into 168-pin edge connector sockets.

Synchronous design allows precise cycle control with the use of

system clock. I/O transactions are possible on every clock cycle.

Range of operating frequencies, programmable latencies allows

the same device to be useful for a variety of high bandwidth,

high performance memory system applications.

FEATURE

• Performance range

Part No.

KMM366S1723T-G8

KMM366S1723T-GH

KMM366S1723T-GL

•

Max Freq. (Speed)

125MHz (8ns @ CL=3)

100MHz (10ns @ CL=2)

100MHz (10ns @ CL=3)

Burst mode operation

Auto & self refresh capability (4096 Cycles/64ms)

LVTTL compatible inputs and outputs

Single 3.3V

0.3V power supply

MRS cycle with address key programs

Latency (Access from column address)

Burst length (1, 2, 4, 8 & Full page)

Data scramble (Sequential & Interleave)

• All inputs are sampled at the positive going edge of the

system clock

• Serial presence detect with EEPROM

• PCB :

Height (1,375mil),

single sided component

PIN CONFIGURATIONS (Front side/back side)

Pin Front Pin

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

*CB0

*CB1

DQM0

Front

Pin Front Pin

Back

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

*CB4

*CB5

CAS

DQM4

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

Back

DQM5

*CS1

RAS

BA0

A11

*CLK1

*A12

CKE0

*CS3

DQM6

DQM7

*A13

*CB6

*CB7

DQ48

DQ49

Pin Back

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

DQ50

DQ51

DQ52

REF

DQ53

DQ54

DQ55

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

*CLK3

**SA0

**SA1

**SA2

29 DQM1 57 DQ18 85

58 DQ19 86

CS0

60 DQ20 88

62 *V

REF

63 *CKE1 91

65 DQ21 93

38 A10/AP 66 DQ22 94

67 DQ23 95

BA1

69 DQ24 97

42 CLK0 70 DQ25 98

71 DQ26 99

72 DQ27 100

101

CS2

46 DQM2 74 DQ28 102

47 DQM3 75 DQ29 103

76 DQ30 104

77 DQ31 105

106

79 CLK2 107

NC 108

52 *CB2 80

WP 109

53 *CB3 81

82 **SDA 110

55 DQ16 83 **SCL 111

112

56 DQ17 84

PIN NAMES

Pin Name

A0 ~ A11

BA0 ~ BA1

DQ0 ~ DQ63

CLK0, CLK2

CKE0

CS0, CS2

RAS

CAS

DQM0 ~ 7

REF

SDA

SCL

SA0 ~ 2

Function

Address input (Multiplexed)

Select bank

Data input/output

Clock input

Clock enable input

Chip select input

Row address strobe

Column address strobe

Write enable

DQM

Power supply (3.3V)

Ground

Power supply for reference

Serial data I/O

Serial clock

Address in EEPROM

Write protection

Don′t use

No connection

* These pins are not used in this module.

These pins should be NC in the system

which does not support SPD.

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

REV. 1 July 1998

KMM366S1723T

PIN CONFIGURATION DESCRIPTION

CLK

Name

System clock

Chip select

Preliminary

PC100 SDRAM MODULE

Input Function

Active on the positive going edge to sample all inputs.

Disables or enables device operation by masking or enabling all inputs except

CLK, CKE and DQM

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one cycle prior to new command.

Disable input buffers for power down in standby.

CKE should be enabled 1CLK+t

prior to valid command.

Row/column addresses are multiplexed on the same pins.

Row address : RA0 ~ RA11, Column address : CA0 ~ CA9

Selects bank to be activated during row address latch time.

Selects bank for read/write during column address latch time.

Latches row addresses on the positive going edge of the CLK with RAS low.

Enables row access & precharge.

Latches column addresses on the positive going edge of the CLK with CAS low.

Enables column access.

Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

Makes data output Hi-Z, t

SHZ

after the clock and masks the output.

Blocks data input when DQM active. (Byte masking)

Data inputs/outputs are multiplexed on the same pins.

WP pin is connected to V

through 47KΩ Resistor.

When WP is "high", EEPROM Programming will be inhibited and the entire memory will

be write-protected.

Power and ground for the input buffers and the core logic.

CKE

Clock enable

A0 ~ A11

BA0 ~ BA1

RAS

CAS

DQM0 ~ 7

DQ0 ~ 63

Address

Bank select address

Row address strobe

Column address strobe

Write enable

Data input/output mask

Data input/output

Write protection

Power supply/ground

REV. 1 July 1998

KMM366S1723T

FUNCTIONAL BLOCK DIAGRAM

CS0

DQM0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQM1

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

CS2

DQM2

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQM3

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

•

DQM4

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQM5

Preliminary

PC100 SDRAM MODULE

DQM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

•

DQM6

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQM7

DQM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

Serial PD

A0 ~ An, BA0 & 1

RAS

CAS

CKE0

10Ω

DQn

Vss

•

Two 0.1uF Capacitors

per each SDRAM

To all SDRAMs

Every DQpin of SDRAM

10Ω

CLK1/3

10pF

3.3pF

SDRAM U0 ~ U7

10Ω

CLK0/2

•

SCL

SDA

•

47KΩ

SA0 SA1 SA2

•

U0/U2

U4/U6

U1/U3

U5/U7

REV. 1 July 1998

KMM366S1723T

ABSOLUTE MAXIMUM RATINGS

Parameter

Voltage on any pin relative to Vss

Voltage on V

supply relative to Vss

Storage temperature

Power dissipation

Short circuit current

Symbol

, V

OUT

, V

DDQ

STG

Preliminary

PC100 SDRAM MODULE

Value

-1.0 ~ 4.6

-55 ~ +150

Unit

°C

Note :

Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS

Recommended operating conditions (Voltage referenced to V

= 0V, T

= 0 to 70°C)

Parameter

Supply voltage

Input logic high voltage

Input logic low voltage

Output logic high voltage

Output logic low voltage

Input leakage current (Inputs)

Input leakage current (I/O pins)

Symbol

, V

DDQ

Min

3.0

2.0

-0.3

2.4

-8

-1.5

Typ

3.3

3.0

Max

3.6

DDQ

+0.3

0.8

0.4

1.5

Unit

= -2mA

= 2mA

3,4

Note

Notes :

1. V

(max) = 5.6V AC. The overshoot voltage duration is

≤

3ns.

2. V

(min) = -2.0V AC. The undershoot voltage duration is

≤

3ns.

3. Any input 0V

≤

DDQ.

Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.

4. Dout is disabled, 0V

≤

OUT

≤

DDQ.

CAPACITANCE

= 3.3V, T

= 23°C, f = 1MHz, V

REF

= 1.4V

200 mV)

Symbol

ADD

CKE

CLK

DQM

OUT

Min

Max

Unit

Address (A0 ~ A11, BA0 ~ BA1)

RAS, CAS, WE

CKE (CKE0)

Clock (CLK0, CLK2)

CS (CS0, CS2)

DQM (DQM0 ~ DQM7)

DQ (DQ0 ~ DQ63)

REV. 1 July 1998

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KMM366S1723T-G8 Related Products

	KMM366S1723T-G8	KMM366S1723T-GH	KMM366S1723T-GL
Description	Synchronous DRAM Module, 16MX64, 6ns, CMOS, DIMM-168	Synchronous DRAM Module, 16MX64, 6ns, CMOS, DIMM-168	Synchronous DRAM Module, 16MX64, 6ns, CMOS, DIMM-168
Maker	SAMSUNG	SAMSUNG	SAMSUNG
Parts packaging code	DIMM	DIMM	DIMM
package instruction	DIMM, DIMM168	DIMM, DIMM168	DIMM, DIMM168
Contacts	168	168	168
Reach Compliance Code	unknown	unknown	unknown
ECCN code	EAR99	EAR99	EAR99
access mode	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
Maximum access time	6 ns	6 ns	6 ns
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	125 MHz	100 MHz	100 MHz
I/O type	COMMON	COMMON	COMMON
JESD-30 code	R-XDMA-N168	R-XDMA-N168	R-XDMA-N168
memory density	1073741824 bit	1073741824 bit	1073741824 bit
Memory IC Type	SYNCHRONOUS DRAM MODULE	SYNCHRONOUS DRAM MODULE	SYNCHRONOUS DRAM MODULE
memory width	64	64	64
Number of functions	1	1	1
Number of ports	1	1	1
Number of terminals	168	168	168
word count	16777216 words	16777216 words	16777216 words
character code	16000000	16000000	16000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C
organize	16MX64	16MX64	16MX64
Output characteristics	3-STATE	3-STATE	3-STATE
Package body material	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED
encapsulated code	DIMM	DIMM	DIMM
Encapsulate equivalent code	DIMM168	DIMM168	DIMM168
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY
power supply	3.3 V	3.3 V	3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified
refresh cycle	4096	4096	4096
self refresh	YES	YES	YES
Maximum standby current	0.008 A	0.008 A	0.008 A
Maximum slew rate	1.6 mA	1.6 mA	1.6 mA
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	3 V	3 V	3 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V
surface mount	NO	NO	NO
technology	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	NO LEAD	NO LEAD	NO LEAD
Terminal pitch	1.27 mm	1.27 mm	1.27 mm
Terminal location	DUAL	DUAL	DUAL

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