PRELIMINARY DATA SHEET
1G bits DDR3 SDRAM
EDJ1104BFBG (256M words
×
4 bits)
EDJ1108BFBG (128M words
×
8 bits)
Specifications
•
Density: 1G bits
•
Organization
⎯
32M words
×
4 bits
×
8 banks (EDJ1104BFBG)
⎯
16M words
×
8 bits
×
8 banks (EDJ1108BFBG)
•
Package
⎯
78-ball FBGA
⎯
Lead-free (RoHS compliant) and Halogen-free
•
Power supply: VDD, VDDQ
=
1.5V
±
0.075V
•
Data rate
⎯
1600Mbps/1333Mbps/1066Mbps (max.)
•
1KB page size
⎯
Row address: A0 to A13
⎯
Column address: A0 to A9, A11 (EDJ1104BFBG)
A0 to A9 (EDJ1108BFBG)
•
Eight internal banks for concurrent operation
•
Interface: SSTL_15
•
Burst lengths (BL): 8 and 4 with Burst Chop (BC)
•
Burst type (BT):
⎯
Sequential (8, 4 with BC)
⎯
Interleave (8, 4 with BC)
•
/CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11
•
/CAS Write Latency (CWL): 5, 6, 7, 8
•
Precharge: auto precharge option for each burst
access
•
Driver strength: RZQ/7, RZQ/6 (RZQ = 240Ω)
•
Refresh: auto-refresh, self-refresh
Features
•
Double-data-rate architecture; two data transfers per
clock cycle
•
The high-speed data transfer is realized by the 8 bits
prefetch pipelined architecture
•
Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
•
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
•
Differential clock inputs (CK and /CK)
•
DLL aligns DQ and DQS transitions with CK
transitions
•
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
•
Data mask (DM) for write data
•
Posted /CAS by programmable additive latency for
better command and data bus efficiency
•
On-Die Termination (ODT) for better signal quality
⎯
Synchronous ODT
⎯
Dynamic ODT
⎯
Asynchronous ODT
•
Multi Purpose Register (MPR) for pre-defined pattern
read out
•
ZQ calibration for DQ drive and ODT
•
Programmable Partial Array Self-Refresh (PASR)
•
/RESET pin for Power-up sequence and reset
function
•
SRT range:
⎯
Normal/extended
•
Programmable Output driver impedance control
•
Refresh cycles
⎯
Average refresh period
7.8µs at 0°C
≤
TC
≤ +85°C
3.9µs at
+85°C <
TC
≤ +95°C
•
Operating case temperature range
⎯
TC = 0°C to +95°C
Document No. E1629E20 (Ver. 2.0)
Date Published July 2010 (K) Japan
Printed in Japan
URL: http://www.elpida.com
©Elpida
Memory, Inc. 2010
EDJ1104BFBG, EDJ1108BFBG
Ordering Information
Part number
EDJ1104BFBG-GL-F
EDJ1104BFBG-GN-F
EDJ1104BFBG-DJ-F
EDJ1104BFBG-AE-F
EDJ1108BFBG-GL-F
EDJ1108BFBG-GN-F
EDJ1108BFBG-DJ-F
EDJ1108BFBG-AE-F
Die
revision
F
Organization
(words
×
bits)
256M
×
4
Internal
banks
8
JEDEC speed bin
(CL-tRCD-tRP)
DDR3-1600J (10-10-10)
DDR3-1600K (11-11-11)
DDR3-1333H (9-9-9)
DDR3-1066F (7-7-7)
DDR3-1600J (10-10-10)
DDR3-1600K (11-11-11)
DDR3-1333H (9-9-9)
DDR3-1066F (7-7-7)
Package
78-ball FBGA
128M
×
8
Part Number
E D J 11 04 B F BG - GL - F
Elpida Memory
Type
D: Monolithic Device
Environment code
F: Lead Free (RoHS compliant)
and Halogen Free
Product Family
J: DDR3
Density / Bank
11: 1Gb / 8-bank
Speed
GL: DDR3-1600J (10-10-10)
GN: DDR3-1600K (11-11-11)
DJ: DDR3-1333H (9-9-9)
AE: DDR3-1066F (7-7-7)
Organization
04: x4
08: x8
Package
BG: FBGA
Power Supply, Interface
B: 1.5V, SSTL_15
Die Rev.
Preliminary Data Sheet E1629E20 (Ver. 2.0)
2
EDJ1104BFBG, EDJ1108BFBG
Pin Configurations
/xxx indicates active low signal.
78-ball FBGA (×4 configuration)
1
A
VSS
B
VSS VSSQ
C
VDDQ
D
VSSQ
E
VREFDQ VDDQ
F
NC
G
ODT
H
NC
J
VSS
K
VDD
L
VSS
M
N
VSS /RESET A13
(Top view)
NC
A8
VSS
VDD
A5
A7
A2
A9
A1
A11
A4
A6
VSS
VDD
M
N
VSS /RESET A13
(Top view)
NC
A8
VSS
A3
A0
A12(/BC) BA1
VDD
L
VSS
VDD
A5
A7
A2
A9
A1
A11
A4
A6
VSS
VDD
BA0
BA2
NC
VREFCA VSS
K
VDD
A3
A0
A12(/BC) BA1
VDD
/CS
/WE
A10(AP)
ZQ
NC
J
VSS
BA0
BA2
NC
VREFCA VSS
VDD
/CAS
/CK
VDD
CKE
H
NC
/CS
/WE
A10(AP)
ZQ
NC
VSS
/RAS
CK
VSS
NC
G
ODT
VDD
/CAS
/CK
VDD
CKE
NC
NC
NC
VDDQ
F
NC
VSS
/RAS
CK
VSS
NC
NC
/DQS
VDD
VSS
VSSQ
E
VREFDQ VDDQ
DQ2
DQS
DQ1
DQ3
VSSQ
D
VSSQ
DQ6
/DQS
DQ4
VDD
DQ7
VSS
DQ5
VSSQ
VDDQ
DQ0
DM
VSSQ VDDQ
C
VDDQ
DQ2
DQS
DQ1
DQ3
VSSQ
VDD
NC
NC
VSS
VDD
B
VSS VSSQ
DQ0
DM/TDQS
VSSQ VDDQ
78-ball FBGA (×8 configuration)
9
A
VSS
VDD
NC
NU/(/TDQS)
VSS
2
3
7
8
1
2
3
7
8
9
VDD
Pin name
A0 to A13*
3
Function
Address inputs
A10 (AP): Auto precharge
A12(/BC): Burst chop
3
Pin name
/RESET*
VDD
VSS
VDDQ
VSSQ
VREFDQ
VREFCA
ZQ
NC*
NU*
1
2
3
Function
Active low asynchronous reset
Supply voltage for internal
circuit
Ground for internal circuit
Supply voltage for DQ circuit
Ground for DQ circuit
Reference voltage for DQ
Reference voltage
Reference pin for ZQ
calibration
No connection
Not usable
BA0 to BA2*
DQ0 to DQ7
DQS, /DQS
Bank select
Data input/output
Differential data strobe
Termination data strobe
Chip select
3
TDQS, /TDQS
/CS*
3
/RAS, /CAS, /WE*
CKE*
3
Command input
Clock enable
Differential clock input
Write data mask
CK, /CK
DM
ODT*
3
ODT control
Notes: 1. Not internally connected with die.
2. Don’t connect. Internally connected.
3. Input only pins (address, command, CKE, ODT and /RESET) do not supply termination.
Preliminary Data Sheet E1629E20 (Ver. 2.0)
3
EDJ1104BFBG, EDJ1108BFBG
CONTENTS
Specifications.................................................................................................................................................1
Features.........................................................................................................................................................1
Ordering Information......................................................................................................................................2
Part Number ..................................................................................................................................................2
Pin Configurations .........................................................................................................................................3
Electrical Conditions ......................................................................................................................................6
Absolute Maximum Ratings .......................................................................................................................... 6
Operating Temperature Condition ................................................................................................................ 6
Recommended DC Operating Conditions (TC = 0°C to +85°C, VDD, VDDQ = 1.5V
±
0.075V) ................... 7
AC and DC Input Measurement Levels (TC = 0°C to +85°C, VDD, VDDQ = 1.5V
±
0.075V)....................... 7
VREF Tolerances ......................................................................................................................................... 8
Input Slew Rate Derating .............................................................................................................................. 9
AC and DC Logic Input Levels for Differential Signals ................................................................................ 15
AC and DC Output Measurement Levels (TC = 0°C to +85°C, VDD, VDDQ = 1.5V
±
0.075V) .................. 20
AC Overshoot/Undershoot Specification..................................................................................................... 22
Output Driver Impedance............................................................................................................................ 23
On-Die Termination (ODT) Levels and I-V Characteristics ......................................................................... 25
ODT Timing Definitions............................................................................................................................... 27
IDD Measurement Conditions (TC = 0°C to +85°C, VDD, VDDQ = 1.5V
±
0.075V) ................................... 31
Electrical Specifications...............................................................................................................................44
DC Characteristics 1 (TC = 0°C to +85°C, VDD, VDDQ = 1.5V
±
0.075V) ................................................. 44
DC Characteristics 2 (TC = 0°C to +85°C, VDD, VDDQ = 1.5V
±
0.075V) ................................................. 45
Pin Capacitance (TC = 25°C, VDD, VDDQ = 1.5V
±
0.075V) ..................................................................... 46
Standard Speed Bins .................................................................................................................................. 47
AC Characteristics (TC = 0°C to +85°C, VDD, VDDQ = 1.5V
±
0.075V, VSS, VSSQ = 0V)....................... 50
Block Diagram .............................................................................................................................................63
Pin Function.................................................................................................................................................64
Command Operation ...................................................................................................................................66
Command Truth Table ................................................................................................................................ 66
CKE Truth Table ......................................................................................................................................... 70
Simplified State Diagram .............................................................................................................................71
RESET and Initialization Procedure ............................................................................................................72
Power-Up and Initialization Sequence ........................................................................................................ 72
Reset and Initialization with Stable Power .................................................................................................. 73
Programming the Mode Register.................................................................................................................74
Mode Register Set Command Cycle Time (tMRD) ..................................................................................... 74
MRS Command to Non-MRS Command Delay (tMOD) ............................................................................. 74
DDR3 SDRAM Mode Register 0 [MR0] ...................................................................................................... 75
DDR3 SDRAM Mode Register 1 [MR1] ...................................................................................................... 76
Preliminary Data Sheet E1629E20 (Ver. 2.0)
4
EDJ1104BFBG, EDJ1108BFBG
DDR3 SDRAM Mode Register 2 [MR2] ...................................................................................................... 77
DDR3 SDRAM Mode Register 3 [MR3] ...................................................................................................... 78
Burst Length (MR0) .................................................................................................................................... 79
Burst Type (MR0) ....................................................................................................................................... 79
DLL Enable (MR1) ...................................................................................................................................... 80
DLL-off Mode .............................................................................................................................................. 80
DLL on/off switching procedure .................................................................................................................. 81
Additive Latency (MR1)............................................................................................................................... 83
Write Leveling (MR1) .................................................................................................................................. 84
TDQS, /TDQS function (MR1) .................................................................................................................... 87
Extended Temperature Usage (MR2) ......................................................................................................... 88
Multi Purpose Register (MR3)..................................................................................................................... 90
Operation of the DDR3 SDRAM ..................................................................................................................97
Read Timing Definition................................................................................................................................ 97
Read Operation ........................................................................................................................................ 101
Write Timing Definition.............................................................................................................................. 108
Write Operation......................................................................................................................................... 109
Write Timing Violations ............................................................................................................................. 115
Write Data Mask ....................................................................................................................................... 116
Precharge ................................................................................................................................................. 117
Auto Precharge Operation ........................................................................................................................ 118
Auto-Refresh............................................................................................................................................. 119
Self-Refresh.............................................................................................................................................. 120
Power-Down Mode ................................................................................................................................... 122
Input Clock Frequency Change during Precharge Power-Down............................................................... 129
On-Die Termination (ODT)........................................................................................................................ 130
ZQ Calibration........................................................................................................................................... 142
Package Drawing ......................................................................................................................................144
78-ball FBGA ............................................................................................................................................ 144
Recommended Soldering Conditions........................................................................................................145
Preliminary Data Sheet E1629E20 (Ver. 2.0)
5
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