PC28F512P30BFA datasheet, PDF - EEWORLD Datasheet

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PC28F512P30BFA: DescriptionFlash, 32MX16, 100ns, PBGA64, 8 X 10 MM, 1.20 MM HEIGHT, LEAD FREE, BGA-64; Categorystorage storage; File Size885KB，82 Pages; ManufacturerNumonyx ( Micron ); Websitehttps://www.micron.com

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Flash, 32MX16, 100ns, PBGA64, 8 X 10 MM, 1.20 MM HEIGHT, LEAD FREE, BGA-64

PC28F512P30BFA Parametric

Parameter Name	Attribute value
Parts packaging code	BGA
package instruction	8 X 10 MM, 1.20 MM HEIGHT, LEAD FREE, BGA-64
Contacts	64
Reach Compliance Code	unknow
ECCN code	3A991.B.1.A
Maximum access time	100 ns
startup block	BOTTOM
JESD-30 code	R-PBGA-B64
length	10 mm
memory density	536870912 bi
Memory IC Type	FLASH
memory width	16
Number of functions	1
Number of terminals	64
word count	33554432 words
character code	32000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	32MX16
Package body material	PLASTIC/EPOXY
encapsulated code	TBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE
Parallel/Serial	PARALLEL
Programming voltage	3 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	2 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
type	NOR TYPE
width	8 mm
Base Number Matches	1

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Numonyx™ Axcell™ P30-65nm Flash Memory

512-Mbit, 1-Gbit Monolithic

Datasheet

Product Features

High performance:

— 100ns initial access time for Easy BGA

— 110ns initial access time for TSOP

— 25ns 16-word asynchronous-page read mode

— 52MHz with zero WAIT states, 17ns clock-to-

data output synchronous-burst read mode

— 4-, 8-, 16- and continuous-word options for

burst mode

— Buffered Enhanced Factory Programming at

2.0MByte/s (typ) using 512-word buffer

— 1.8V buffered programming at 1.46MByte/s

(Typ) using 512-word buffer

Architecture:

— Multi-Level Cell Technology: Highest Density

at Lowest Cost

Enhanced Security:

— Absolute write protection: VPP = VSS

— Power-transition erase/program lockout

— Individual zero-latency block locking

— Individual block lock-down capability

— Password Access feature

— One-Time Programmable Register:

— 64 OTP bits, programmed with unique

information by Numonyx

— 2112 OTP bits, available for customer

programming

Software:

— 20µs (Typ) program suspend

— 20µs (Typ) erase suspend

— Numonyx™ Flash Data Integrator optimized

— Basic Command Set and Extended Function

Interface (EFI) Command Set compatible

— Common Flash Interface capable

Density and Packaging

— 56-Lead TSOP (512-Mbit, 1-Gbit)

— 64-Ball Easy BGA (512-Mbit, 1-Gbit)

— 16-bit wide data bus

Quality and Reliability

— Operating temperature: –40°C to +85°C

— Minimum 100,000 erase cycles

— Numonyx™ ETOX™ X process technology

— Symmetrically-blocked architecture

— Asymmetrically-blocked architecture, Four

32-KByte parameter blocks: Top or Bottom

configuration

—

128-KByte array blocks

— Blank Check to verify an erase block

Voltage and Power:

— VCC (core) voltage: 1.7V – 2.0V

— VCCQ (I/O) voltage: 1.7V – 3.6V

— Standby current: 70µA(Typ) for 512-Mbit,

75µA(Typ) for 1-Gbit

— Continuous synchronous read current: 21mA

(Typ)/24mA (Max) at 52MHz

Datasheet

Aug 2009

Order Number: 208042-02

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR

OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND

CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED

WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A

PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx

products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.

Legal Lines and Disclaimers

Numonyx may make changes to specifications and product descriptions at any time, without notice.

Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the

presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel

or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting

Numonyx's website at

http://www.numonyx.com.

Numonyx, the Numonyx logo, and Axcell are trademarks or registered trademarks of Numonyx , B.V. or its subsidiaries in other countries.

*Other names and brands may be claimed as the property of others.

Datasheet

Aug 2009

Order Number: 208042-02

P30-65nm

Contents

1.0

Functional Description

............................................................................................... 5

1.1

Introduction ....................................................................................................... 5

1.2

Overview ........................................................................................................... 5

1.3

Memory Map....................................................................................................... 6

Package Information

................................................................................................. 7

2.1

56-Lead TSOP..................................................................................................... 7

2.2

64-Ball Easy BGA Package .................................................................................... 8

Ballouts

................................................................................................................... 10

Signals

.................................................................................................................... 12

Bus Operations

........................................................................................................ 13

5.1

Read - Asynchronous Mode................................................................................. 13

5.2

Read - Synchronous Mode .................................................................................. 13

5.3

Write ............................................................................................................... 14

5.4

Output Disable .................................................................................................. 14

5.5

Standby ........................................................................................................... 14

5.6

Reset............................................................................................................... 15

Command Set

.......................................................................................................... 16

6.1

Device Command Codes ..................................................................................... 16

6.2

Device Command Bus Cycles .............................................................................. 17

Read

7.1

7.2

7.3

7.4

7.5

Operation........................................................................................................

Read Array ....................................................................................................... 19

Read Device Identifier........................................................................................ 19

Read CFI .......................................................................................................... 20

Read Status Register ......................................................................................... 20

Clear Status Register ......................................................................................... 20

2.0

3.0

4.0

5.0

6.0

7.0

8.0

Program Operation

.................................................................................................. 21

8.1

Word Programming ........................................................................................... 21

8.2

Buffered Programming ....................................................................................... 21

8.3

Buffered Enhanced Factory Programming.............................................................. 22

8.4

Program Suspend .............................................................................................. 24

8.5

Program Resume............................................................................................... 25

8.6

Program Protection............................................................................................ 25

Erase Operation.......................................................................................................

9.1

Block Erase ...................................................................................................... 26

9.2

Blank Check ..................................................................................................... 26

9.3

Erase Suspend .................................................................................................. 27

9.4

Erase Resume................................................................................................... 27

9.5

Erase Protection ................................................................................................ 27

9.0

10.0 Security

................................................................................................................... 28

10.1 Block Locking.................................................................................................... 28

10.2 Selectable OTP Blocks ........................................................................................ 30

10.3 Password Access ............................................................................................... 30

11.0 Register...................................................................................................................

11.1 Status Register (SR) .......................................................................................... 31

11.2 Read Configuration Register (RCR) ...................................................................... 32

11.3 One-Time Programmable (OTP) Registers ............................................................. 38

Datasheet

Aug 2009

Order Number: 208042-02

P30-65nm

12.0 Power and Reset Specifications

...............................................................................41

12.1 Power-Up and Power-Down .................................................................................41

12.2 Reset Specifications ...........................................................................................41

12.3 Power Supply Decoupling....................................................................................42

13.0 Maximum Ratings and Operating Conditions

............................................................43

13.1 Absolute Maximum Ratings .................................................................................43

13.2 Operating Conditions..........................................................................................43

14.0 Electrical Specifications

...........................................................................................44

14.1 DC Current Characteristics ..................................................................................44

14.2 DC Voltage Characteristics ..................................................................................45

15.0 AC Characteristics

....................................................................................................46

15.1 AC Test Conditions.............................................................................................46

15.2 Capacitance ......................................................................................................47

15.3 AC Read Specifications ......................................................................................48

15.4 AC Write Specifications .......................................................................................52

15.5 Program and Erase Characteristics .......................................................................56

16.0 Ordering Information...............................................................................................57

Supplemental Reference Information.......................................................................58

Conventions - Additional Documentation

.................................................................82

Revision History.......................................................................................................83

Datasheet

Aug 2009

Order Number: 208042-02

P30-65nm

1.0

1.1

Functional Description

Introduction

This document provides information about the Numonyx

Axcell

P30-65nm Flash

memory and describes its features, operations, and specifications.

P30-65nm is the latest generation of Numonyx

Axcell

P30 Flash memory to the

embedded flash market segment, offered in 64-Mbit up through 2-Gbit. This document

covers specifically 512-Mbit and 1-Gbit product information. Benefits include more

density in less space, high-speed interface NOR device, and support for code and data

storage. Features include high-performance synchronous-burst read mode, a

dramatical improvement in buffer program time through larger buffer size, fast

asynchronous access times, low power, flexible security options, and two industry-

standard package choices.

P30-65nm is manufactured using Numonyx™ 65nm ETOX™ X process technology.

1.2

Overview

P30-65nm device provides high performance on a 16-bit data bus. Individually erasable

memory blocks are sized for optimum code and data storage. Upon initial power-up or

return from reset, the device defaults to asynchronous page-mode read. Configuring

the Read Configuration Register (RCR) enables synchronous burst-mode reads. In

synchronous burst mode, output data is synchronized with a user-supplied clock signal.

A WAIT signal provides easy CPU-to-flash memory synchronization.

In addition to the enhanced architecture and interface, the device incorporates

technology that enables fast buffer program and erase operations. The device features

a 512-word buffer to enable optimum programming performance, which can improve

system programming throughput time significantly to 1.46MByte/s.

Designed for low-voltage systems, the P30-65nm device supports read operations with

VCC at 1.8V, and erase and program operations with VPP at 1.8V or 9.0V. Buffered

Enhanced Factory Programming provides the fastest flash array programming

performance with VPP at 9.0V, which increases factory throughput. With VPP at 1.8V,

VCC and VPP can be tied together for a simple, ultra low power design. In addition to

voltage flexibility, a dedicated VPP connection provides complete data protection when

VPP

≤

PPLK

The Command User Interface is the interface between the system processor and all

internal operations of the device. An internal Write State Machine automatically

executes the algorithms and timings necessary for block erase and program. A Status

A device command sequence invokes program and erase automation. Each erase

operation erases one block. The Erase Suspend feature allows system software to

pause an erase cycle to read or program data in another block. Program Suspend

allows system software to pause programming to read other locations.

P30-65nm OTP register allows unique flash device identification that can be used to

increase system security. The individual Block Lock feature provides zero-latency block

locking and unlocking. The P30-65nm device adds enhanced protection via Password

Access; this new feature allows write and/or read access protection of user-defined

blocks. In addition, the P30-65nm device also has backward compatible One-Time

Programmable (OTP) permanent block locking security feature.

Datasheet

Aug 2009

Order Number:208042-02

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