Preliminary
TSC3D472C09/18/36-333/300/250/200/167
72Mb Synchronous Double Transfer Rate 3T-iRAM™
With Common I/O
Burst of 4
SRAM-Compatible
Features
Error-resistant 3T-iRAM™ technology
DDR-II Interface with Common I/O bus
JEDEC-standard pinout and package
Burst of 4 Read and Write (Byte Writes)
1.8 V +100/–100 mV core power supply
1.5 V or 1.8 V HSTL Interface
Pipelined read operation with self-timed Late Write
Fully coherent read and write pipelines
ZQ pin for programmable output drive strength
IEEE 1149.1 JTAG-compliant Boundary Scan
165-bump 15mm x 17mm BGA, 1 mm bump pitch
Pin-compatible with 9Mb, 18Mb, 36Mb, and 144Mb
devices
Functional Description
3T-iRAM™ is a unique type of dynamic memory. Tezzaron
has crafted these pseudo-static devices to provide entirely
SRAM-compatible interfaces and timing. The unique design
of these 3T memories provides soft error rates up to 10
times lower than equivalent high-speed, high-density
SRAMs.
These synchronous 72Mb 3T-iRAM devices are drop-in
compatible with comparable SRAM devices. They employ
two input register clocks, K and
K
. The user can
manipulate the output register clocks quasi-independently
with C and
C
. These clocks are four independent single-
ended clock inputs, not differential inputs. If the C clocks are
tied high, the K clocks are routed internally to fire the output
registers instead.
These devices always transfer data in four packets, but
addressing is handled differently for x9 parts than for x36
and x18 parts:
For x36 and x18, when a new address is loaded, A0
and A1 preset an internal 2 bit address counter. The
counter increments by 1 for each beat of a burst of four
data transfer, wrapping to 00 after reaching 11.
For x9, when a new address is loaded, the LSBs are
internally set to 00 for the first read or write transfer,
and incremented by 1 for the next three transfers.
Because the LSBs are tied off internally, the address
field of a TSC3D472C09 is two address pins less than
the advertised index depth – i.e., it has a 2048K
addressable index.
Options
Configurations:
8M x 9
4M x 18
2M x 36
333 MHz
300 MHz
200 MHz
167 MHz
Marking
C09
C18
C36
-333
-300
-200
-167
Speed (MHz):
Part number example:
TSC3D472C18-300
Speed Parameter Synopsis:
(all units ns)
tKHKH
tKHQV
-333
3.00
0.45
-300
3.30
0.45
-250
4.00
0.45
-200
5.00
0.45
-167
6.00
0.50
Rev. 1.0 – September 13, 2006
Page 1 of 30
©2006, Tezzaron Semiconductor Corp.
Preliminary
TSC3D472C09/18/36-333/300/250/200/167
2M x 36: Top View
11 x 15 Bump BGA – 13 x 15 mm2 Body – 1 mm Bump Pitch
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
2
NC
DQ27
NC
DQ29
NC
DQ30
DQ31
V
REF
NC
NC
DQ33
NC
DQ35
NC
TCK
3
SA
DQ18
DQ28
DQ19
DQ20
DQ21
DQ22
V
DDQ
DQ32
DQ23
DQ24
DQ34
DQ25
DQ26
SA
4
R/
W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
6
7
8
9
SA
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
SA
10
SA
NC
DQ17
NC
DQ15
NC
NC
V
REF
DQ13
DQ12
NC
DQ11
NC
DQ9
TMS
11
CQ
DQ8
DQ7
DQ16
DQ6
DQ5
DQ14
ZQ
DQ4
DQ3
DQ2
DQ1
DQ10
DQ0
TDI
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
BW 2
BW 3
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
K
K
SA0
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
BW1
BW 0
SA1
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
LD
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
Doff
NC
NC
NC
NC
NC
NC
TDO
C
Notes:
BW 0
controls writes to DQ0:DQ8;
BW1
controls writes to DQ9:DQ17;
BW 2
controls writes to DQ18:DQ26;
BW 3
controls writes to DQ27:DQ35.
Rev. 1.0 – September 13, 2006
Page 2 of 30
©2006, Tezzaron Semiconductor Corp.
Preliminary
TSC3D472C09/18/36-333/300/250/200/167
4M x 18: Top View
11 x 15 Bump BGA – 13 x 15 mm2 Body – 1 mm Bump Pitch
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
2
SA
DQ9
NC
NC
NC
DQ12
NC
V
REF
NC
NC
DQ15
NC
NC
NC
TCK
3
SA
NC
NC
DQ10
DQ11
NC
DQ13
V
DDQ
NC
DQ14
NC
NC
DQ16
DQ17
SA
4
R/
W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
6
7
NC
8
9
SA
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
SA
10
SA
NC
DQ7
NC
NC
NC
NC
V
REF
DQ4
NC
NC
DQ1
NC
NC
TMS
11
CQ
DQ8
NC
NC
DQ6
DQ5
NC
ZQ
NC
DQ3
DQ2
NC
NC
DQ0
TDI
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
BW1
NC
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
K
K
SA0
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
LD
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
BW 0
SA1
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
Doff
NC
NC
NC
NC
NC
NC
TDO
C
Notes:
BW 0
controls writes to DQ0:DQ8;
BW1
controls writes to DQ9:DQ17
Rev. 1.0 – September 13, 2006
Page 3 of 30
©2006, Tezzaron Semiconductor Corp.
Preliminary
TSC3D472C09/18/36-333/300/250/200/167
8M x 9: Top View
11 x 15 Bump BGA – 13 x 15 mm2 Body – 1 mm Bump Pitch
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
2
SA
NC
NC
NC
NC
NC
NC
V
REF
NC
NC
DQ7
NC
NC
NC
TCK
3
SA
NC
NC
NC
DQ5
NC
DQ6
V
DDQ
NC
NC
NC
NC
NC
DQ8
SA
4
R/
W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
NC
NC
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
7
NC
8
9
SA
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
SA
10
SA
NC
NC
NC
NC
NC
NC
V
REF
DQ2
NC
NC
NC
NC
NC
TMS
11
CQ
DQ4
NC
NC
DQ3
NC
NC
ZQ
NC
NC
DQ1
NC
NC
DQ0
TDI
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
K
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
LD
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
BW
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
Doff
NC
NC
NC
NC
NC
NC
TDO
C
Notes:
Unlike the x36 and x18 versions of this device, the x9 does not give the user access to address bits 0 and 1.
The least significant address bits are set to 00 at the beginning of each access.
Rev. 1.0 – September 13, 2006
Page 4 of 30
©2006, Tezzaron Semiconductor Corp.
Preliminary
TSC3D472C09/18/36-333/300/250/200/167
Pin Descriptions
Symbol
SA
SA0, SA1
NC
R/
W
Type
I
NPUT
I
NPUT
---
I
NPUT
I
NPUT
I
NPUT
I
NPUT
I
NPUT
I
NPUT
I
NPUT
I
NPUT
O
UTPUT
I
NPUT
I
NPUT
I/O
I
NPUT
O
UTPUT
S
UPPLY
S
UPPLY
S
UPPLY
Description
Synchronous address inputs
Least significant address bits
For x36 and x18: user input to the burst counter
For x9: internally set to 00
No connect; not connected to die or any other pin
Synchronous read/write
Byte write controls
Synchronous load
Input clocks (positive/negative)
Output clocks (positive/negative)
Test mode select
Test data input
Test clock
Test data output
HSTL input reference voltage
Output impedance matching input
Data; three-state
Disable DLL (when low)
Output echo clock (positive/negative)
Power supply; 1.8 V nominal
Isolated output buffer supply; 1.5 V nominal
Ground
BW 0
–
BW 3
LD
K/
K
C/
C
TMS
TDI
TCK
TDO
V
REF
ZQ
DQ
Doff
CQ /
CQ
V
DD
V
DDQ
V
SS
Functional Details
Background
Common I/O SRAMs, from a system architecture point of view, are attractive in read dominated or block transfer
applications. Therefore, this device’s interface and truth table are optimized for burst reads and writes. Common I/O
SRAMs are unpopular in applications where alternating reads and writes are needed because bus turnaround delays can
cut high speed Common I/O SRAM data bandwidth in half.
Burst Operations
Read and write operations are "burst" operations. In every case where a read or write command is accepted by the RAM,
it responds by issuing or accepting four beats of data, executing a data transfer on subsequent rising clock edges, as
illustrated in the timing diagrams. It is not possible to stop a burst once it starts; four beats of data are always transferred.
This means that it is possible to load new addresses every other K clock cycle. Addresses can be loaded less often, if
intervening deselect cycles are inserted.
Deselect Cycles
Chip Deselect commands are pipelined to the same degree as read commands. This means that if a deselect command
is applied to the RAM on the next cycle after a read command, the device will complete the four beat read data transfer
and then execute the deselect command, returning the output drivers to high-Z. A high on the
LD
pin prevents any read
or write commands and puts the RAM into deselect mode as soon as it completes any outstanding burst transfer
operations.
Rev. 1.0 – September 13, 2006
Page 5 of 30
©2006, Tezzaron Semiconductor Corp.
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