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TSC3D472C36-200

Description
SRAM
Categorystorage    storage   
File Size528KB,30 Pages
ManufacturerTezzaron Semiconductor Corp.
Download Datasheet Parametric Compare View All

TSC3D472C36-200 Overview

SRAM

TSC3D472C36-200 Parametric

Parameter NameAttribute value
MakerTezzaron Semiconductor Corp.
package instruction,
Reach Compliance Codeunknown
Preliminary
TSC3D472C09/18/36-333/300/250/200/167
72Mb Synchronous Double Transfer Rate 3T-iRAM™
With Common I/O
Burst of 4
SRAM-Compatible
Features
ƒ
Error-resistant 3T-iRAM™ technology
ƒ
DDR-II Interface with Common I/O bus
ƒ
JEDEC-standard pinout and package
ƒ
Burst of 4 Read and Write (Byte Writes)
ƒ
1.8 V +100/–100 mV core power supply
ƒ
1.5 V or 1.8 V HSTL Interface
ƒ
Pipelined read operation with self-timed Late Write
ƒ
Fully coherent read and write pipelines
ƒ
ZQ pin for programmable output drive strength
ƒ
IEEE 1149.1 JTAG-compliant Boundary Scan
ƒ
165-bump 15mm x 17mm BGA, 1 mm bump pitch
ƒ
Pin-compatible with 9Mb, 18Mb, 36Mb, and 144Mb
devices
Functional Description
3T-iRAM™ is a unique type of dynamic memory. Tezzaron
has crafted these pseudo-static devices to provide entirely
SRAM-compatible interfaces and timing. The unique design
of these 3T memories provides soft error rates up to 10
times lower than equivalent high-speed, high-density
SRAMs.
These synchronous 72Mb 3T-iRAM devices are drop-in
compatible with comparable SRAM devices. They employ
two input register clocks, K and
K
. The user can
manipulate the output register clocks quasi-independently
with C and
C
. These clocks are four independent single-
ended clock inputs, not differential inputs. If the C clocks are
tied high, the K clocks are routed internally to fire the output
registers instead.
These devices always transfer data in four packets, but
addressing is handled differently for x9 parts than for x36
and x18 parts:
For x36 and x18, when a new address is loaded, A0
and A1 preset an internal 2 bit address counter. The
counter increments by 1 for each beat of a burst of four
data transfer, wrapping to 00 after reaching 11.
For x9, when a new address is loaded, the LSBs are
internally set to 00 for the first read or write transfer,
and incremented by 1 for the next three transfers.
Because the LSBs are tied off internally, the address
field of a TSC3D472C09 is two address pins less than
the advertised index depth – i.e., it has a 2048K
addressable index.
Options
ƒ
Configurations:
8M x 9
4M x 18
2M x 36
333 MHz
300 MHz
200 MHz
167 MHz
Marking
C09
C18
C36
-333
-300
-200
-167
ƒ
Speed (MHz):
Part number example:
TSC3D472C18-300
Speed Parameter Synopsis:
(all units ns)
tKHKH
tKHQV
-333
3.00
0.45
-300
3.30
0.45
-250
4.00
0.45
-200
5.00
0.45
-167
6.00
0.50
Rev. 1.0 – September 13, 2006
Page 1 of 30
©2006, Tezzaron Semiconductor Corp.

TSC3D472C36-200 Related Products

TSC3D472C36-200 TSC3D472C36-300 TSC3D472C36-333 TSC3D472C09-300 TSC3D472C09-200 TSC3D472C09-250 TSC3D472C18-300 TSC3D472C36-250
Description SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAM
Maker Tezzaron Semiconductor Corp. Tezzaron Semiconductor Corp. Tezzaron Semiconductor Corp. Tezzaron Semiconductor Corp. Tezzaron Semiconductor Corp. Tezzaron Semiconductor Corp. Tezzaron Semiconductor Corp. Tezzaron Semiconductor Corp.
Reach Compliance Code unknown unknown unknown unknown unknown unknown unknown unknown
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