K3P4V(U)1000E-D(G)C
8M-Bit (1Mx8/ 512Kx16) CMOS MASK ROM
FEATURES
•
Switchable organization
1,048,576 x 8(byte mode)
524,288 x 16(word mode)
•
Fast access time
Random Access Time/Page Access Time
3.3V Operation : 100/30ns(Max.)@C
L
=50pF,
120/40ns(Max.)@C
L
=100pF
3.0V Operation : 120/40ns(Max.)@C
L
=100pF
4 Words / 8 Bytes page access
•
Supply voltage : single +3.0V/ single +3.3V
•
Current consumption
Operating : 40mA(Max.)
Standby : 30
µA(Max.)
•
Fully static operation
•
All inputs and outputs TTL compatible
•
Three state outputs
•
Package
-. K3P4V(U)1000E-DC : 42-DIP-600
-. K3P4V(U)1000E-GC : 44-SOP-600
CMOS MASK ROM
GENERAL DESCRIPTION
The K3P4V(U)1000E-D(G)C is a fully static mask programma-
ble ROM fabricated using silicon gate CMOS process technol-
ogy, and is organized either as 1,048,576 x 8(byte mode) or as
524,288 x 16(word mode) depending on BHE voltage level.(See
mode selection table)
This device includes page read mode function, page read mode
allows 4 words (or 8 bytes) of data to read fast in the same
page, CE and A
2
~ A
18
should not be changed.
This device operates with 3.0V or 3.3V power supply, and all
inputs and outputs are TTL compatible.
Because of its asynchronous operation, it requires no external
clock assuring extremely easy operation.
It is suitable for use in program memory of microprocessor, and
data memory, character generator.
The K3P4V(U)1000E-DC is packaged in a 42-DIP and the
K3P4V(U)1000E-GC in a 44-SOP.
FUNCTIONAL BLOCK DIAGRAM
A
18
.
.
.
.
.
.
.
.
A
2
A
0~
A
1
A
-1
PIN CONFIGURATION
A
18
A
17
A
7
A
6
A
5
A
4
A
3
1
2
3
4
5
6
7
8
42 N.C
41 A
8
40 A
9
39 A
10
38 A
11
37 A
12
36 A
13
35 A
14
34 A
15
33 A
16
32 BHE
31 V
S S
N.C 1
A
18
2
A
17
A
7
3
4
44 N.C
43 N.C
42 A
8
41 A
9
40 A
10
39 A
11
38 A
12
37 A
13
36 A
14
35 A
15
34 A
16
33 BHE
32 V
S S
31 Q
15
/A
-1
30 Q
7
29 Q
14
28 Q
6
27 Q
13
26 Q
5
25 Q
12
24 Q
4
23 V
CC
X
BUFFERS
AND
DECODER
MEMORY CELL
MATRIX
(524,288x16/
1,048,576x8)
A
6
5
A
5
6
A
4
7
A
3
8
A
2
9
A
1
10
A
0
11
12
13
14
15
16
17
18
19
20
21
22
Y
BUFFERS
AND
DECODER
SENSE AMP.
DATA OUT
BUFFERS
. . .
9
A
0
10
CE 11
V
SS
12
OE 13
Q
0
14
Q
8
15
Q
1
16
Q
9
17
Q
2
18
Q
10
19
Q
3
20
Q
11
21
A
2
A
1
DIP
CE
OE
BHE
Pin Name
A
0
- A
1
A
2
- A
18
Q
0
- Q
14
Q
15
/A
-1
BHE
CE
OE
V
CC
V
SS
N.C
Pin Function
Page Address Inputs
Address Inputs
Data Outputs
Output 15(Word mode)/
LSB Address(Byte mode)
Word/Byte selection
Chip Enable
Output Enable
Power
Ground
No Connection
CONTROL
LOGIC
Q
0
/Q
8
Q
7
/Q
15
CE
30 Q
15
/A
-1
V
S S
29 Q
7
OE
28 Q
14
Q
0
27 Q
6
Q
8
26 Q
13
Q
1
25 Q
5
Q
9
24 Q
12
Q
2
23 Q
4
Q
10
22 V
CC
Q
3
Q
11
SOP
K3P4V(U)1000E-DC
K3P4V(U)1000E-GC
K3P4V(U)1000E-D(G)C
ABSOLUTE MAXIMUM RATINGS
Item
Voltage on Any Pin Relative to V
SS
Temperature Under Bias
Storage Temperature
Symbol
V
IN
T
BIAS
T
Stg
Rating
CMOS MASK ROM
Unit
V
°
C
°
C
-0.3 to +4.5
-10 to +85
-55 to +150
NOTE
: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to th e
conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to V
SS
, T
A
=0 to 70°C)
Item
Supply Voltage
Supply Voltage
Symbol
V
CC
V
SS
Min
2.7/3.0
0
Typ
3.0/3.3
0
Max
3.3/3.6
0
Unit
V
V
DC CHARACTERISTICS
Parameter
Operating Current
Standby Current(TTL)
Standby Current(CMOS)
Input Leakage Current
Output Leakage Current
Input High Voltage, All Inputs
Input Low Voltage, All Inputs
Output High Voltage Level
Output Low Voltage Level
Symbol
I
CC
I
SB1
I
SB2
I
LI
I
LO
V
IH
V
IL
V
OH
V
OL
I
OH
=-400
µA
I
OL
=2.1mA
Test Conditions
Cycle=5MHz, all outputs open, CE =OE=V
IL
,
V
IN
=0.45V to 2.4V (AC Test Condition)
CE=V
IH
, all outputs open
CE=V
CC
, all outputs open
V
IN
=0 to V
CC
V
OUT
=0 to V
CC
-
-
2.0
-0.3
2.4
-
V
CC
=3.3V±0.3V
V
CC
=3.0V±0.3V
Min
-
Max
40
35
500
30
10
10
V
CC
+0.3
0.6
-
0.4
Unit
mA
mA
µA
µA
µA
µA
V
V
V
V
NOTE
: Minimum DC Voltage(V
IL
) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns.
Maximum DC voltage on input pins(V
IH
) is V
C C
+0.3V which, during transitions, may overshoot to V
C C
+2.0V for periods <20ns.
MODE SELECTION
CE
H
L
L
OE
X
H
L
L
Input
Operating
BHE
X
X
H
Q
15
/A
-1
X
X
Output
Mode
Standby
Operating
Operating
Data
High-Z
High-Z
Q
0
~Q
15
: Dout
Q
0
~Q
7
: Dout
Q
8
~Q
14
: Hi-Z
Power
Standby
Active
Active
Active
CAPACITANCE
(T
A
=25°C, f=1.0MHz)
Item
Output Capacitance
Input Capacitance
Symbol
C
OUT
C
IN
Test Conditions
V
OUT
=0V
V
IN
=0V
Min
-
-
Max
12
12
Unit
pF
pF
NOTE
: Capacitance is periodically sampled and not 100% tested.
K3P4V(U)1000E-D(G)C
TEST CONDITIONS
Item
Input Pulse Levels
Input Rise and Fall Times
Input and Output timing Levels
Output Loads
Value
CMOS MASK ROM
AC CHARACTERISTICS
(T
A
=0°C to +70°C, V
CC
=3.3V/3.0V±0.3V, unless otherwise noted.)
0.45V to 2.4V
10ns
1.5V
1 TTL Gate and C
L
=50pF or 100pF
READ CYCLE
Item
Symbol
K3P4V1000E-D(G)C10
(C
L
=50pF)
Min
Read Cycle Time
Chip Enable Access Time
Address Access Time
Page Address Access Time
Output Enable Access Time
Output or Chip Disable to
Output High-Z
Output Hold from Address
t
RC
t
ACE
t
AA
t
PA
t
OE
t
DF
t
OH
0
100
100
100
30
30
20
0
Max
K3P4V1000E-D(G)C12
(C
L
=100pF)
Min
120
120
120
40
40
20
0
Max
K3P4U1000E-D(G)C12
(C
L
=100pF)
Min
120
120
120
40
40
20
Max
ns
ns
ns
ns
ns
ns
ns
Unit
NOTE
: Page Address is determined as below.
Word mode(BHE=V
IH
) ; A
0
, A
1
Byte mode(BHE=V
IL
) ; A
-1
, A
0
, A
1
MCU
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