LXT380BE datasheet, PDF - EEWORLD Datasheet

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LXT380BE: DescriptionPCM Transceiver, 1-Func, PBGA160, PLASTIC, BGA-160; CategoryWireless rf/communication Telecom circuit; File Size905KB，68 Pages; ManufacturerCortina Systems Inc

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LXT380BE Overview

PCM Transceiver, 1-Func, PBGA160, PLASTIC, BGA-160

LXT380BE Parametric

Parameter Name	Attribute value
Maker	Cortina Systems Inc
Objectid	2146528235
Parts packaging code	BGA
package instruction	BGA,
Contacts	160
Reach Compliance Code	compliant
compound_id	6923421
JESD-30 code	S-PBGA-B160
length	15 mm
Number of functions	1
Number of terminals	160
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Certification status	Not Qualified
Maximum seat height	1.8 mm
Nominal supply voltage	3.3 V
surface mount	YES
Telecom integrated circuit types	PCM TRANSCEIVER
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	15 mm

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LXT380

Octal E1 Line Interface Unit

Datasheet

The LXT380 is an octal short haul Pulse Code Modulation (PCM) Line Interface Unit for ITU

G.703 2.048 Mbit/sec. transmission systems. It incorporates eight independent receivers and

eight independent transmitters in a single LQFP-144 or PBGA-160 package.

The transmit drivers maintain low impedance output during marks and spaces. The drivers also

provide constant pulse amplitudes independent of any supply voltage variations. The LXT380

may be configured for unbalanced 75

Ω

or for balanced 120

Ω

systems without external

component changes and exceeds latest ETSI return loss recommendations. An on chip pulse

shaping circuit generates accurate transmit pulses independent of the transmit clock duty cycle.

The LXT380 features a differential data receiver architecture with high noise interference

margin and uses peak detection and a variable threshold for reliable data recovery down to 500

mV or up to 12 dB of cable attenuation. The fully digital clock recovery PLL is referenced to a

low frequency master clock of 2.048MHz. Each receiver incorporates an analog/digital Loss Of

Signal (LOS) processor. The LXT380 features a "smart power" driver failure monitoring circuit

in parallel to TTIP and TRING that reports secondary line shorts.

In addition, the LXT380 can be configured as 7 channel transceiver for Synchronous Digital

Hierarchy (SDH) tributary port cards with G.772 compliant non intrusive protected monitoring

points.

The fast power down mode of all transmitters allows the implementation of Hitless Protection

Switching (HPS) application without the use of relays.

Product Features

Octal E1 short haul transceiver per ITU

G.703

Single rail supply voltage of 3.3V with 5V

I/O capability

Low power consumption of <100mW per

channel (typ.)

Ω

/120

Ω

TX operation without

component changes

Hitless Protection Switching (HPS)

Driver short circuit current limiter (<50 mA

RMS)

Transmit return loss exceeds ETSI ETS

300166

Selectable transmit pulse shape PLL

Per channel clock recovery

Selectable HDB3 line encoder/decoder

On chip secondary driver short circuit

monitoring circuit

Provides protected monitoring points per

ITU G.772

Analog/digital and remote loopback testing

function

LOS per ITU G.775 and ETS 300 233

(selectable)

8 bit parallel or 4 wire serial control

interface

JTAG Boundary Scan test port per IEEE

1149.4

Small footprint 144 Pin LQFP & 160 Pin

PBGA Packages

As of January 15, 2001, this document replaces the Level One document

known as

Octal E1 G.703 Transceiver.

Order Number: 248995-001

January 2001

Octal E1 Line Interface Unit — LXT380

Contents

1.0

2.0

Pin Assignments and Signal Descriptions

...................................................... 9

Functional Description

...........................................................................................21

2.1

2.2

Initialization..........................................................................................................21

2.1.1 Reset Operation .....................................................................................21

Receiver ..............................................................................................................21

2.2.1 Loss Of Signal Detector .........................................................................22

2.2.1.1 Clock and Data Recovery Mode................................................22

2.2.1.2 Data Recovery Mode.................................................................22

In Service Code Violation Monitoring ..................................................................22

Transmitter ..........................................................................................................23

2.4.1 Transmit Pulse Shaping .........................................................................23

Line Protection ....................................................................................................24

Driver Failure Monitor..........................................................................................25

Loopbacks ...........................................................................................................25

2.7.1 Analog Loopback....................................................................................25

2.7.2 Digital Loopback.....................................................................................26

2.7.3 Remote Loopback ..................................................................................26

2.7.4 Transmit All Ones (TAOS)......................................................................27

G.772 Monitoring.................................................................................................28

Hitless Protection Switching (HPS) .....................................................................28

Operation Mode Summary ..................................................................................28

Interfacing with 5V logic ......................................................................................29

Parallel Host Interface .........................................................................................29

2.12.1 Motorola Interface ..................................................................................30

2.12.2 Intel Interface..........................................................................................30

Interrupt Handling................................................................................................31

2.13.1 Interrupt Sources....................................................................................31

2.13.2 Interrupt Enable......................................................................................31

2.13.3 Interrupt Clear ........................................................................................31

Serial Host Mode.................................................................................................32

2.3

2.4

2.5

2.6

2.7

2.8

2.9

2.10

2.11

2.12

2.13

2.14

3.0

4.0

.............................................................................................33

JTAG Boundary Scan

.............................................................................................37

4.1

4.2

4.3

4.4

Overview .............................................................................................................37

Architecture .........................................................................................................37

TAP Controller.....................................................................................................38

JTAG Register Description..................................................................................40

4.4.1 Boundary Scan Register, BSR ...............................................................40

4.4.2 Device Identification Register, IDR.........................................................43

4.4.3 Bypass Register, BYR............................................................................43

4.4.4 Analog Port Scan Register, ASR............................................................44

4.4.5 Instruction Register, IR...........................................................................45

Recommendations and Specifications ................................................................65

5.0

Test Specifications

..................................................................................................46

5.1

Datasheet

LXT380 — Octal E1 Line Interface Unit

6.0

Mechanical Specifications

................................................................................... 66

Figures

LXT380 Block Diagram ......................................................................................... 7

LXT380 Detailed Block Diagram ........................................................................... 8

LXT380 Low-Profile Quad Flat Package (LQFP) Pin Assignments ...................... 9

LXT380 Plastic Ball Grid Array (PBGA) Package Pin Assignments ................... 10

50% AMI Coding ................................................................................................. 23

External Transmit/Receive Line Circuitry ............................................................ 24

Analog Loopback ................................................................................................ 25

Digital Loopback.................................................................................................. 26

Remote Loopback ............................................................................................... 26

TAOS Data Path ................................................................................................. 27

TAOS with Digital Loopback ............................................................................... 27

TAOS with Analog Loopback .............................................................................. 27

Serial Host Mode Timing..................................................................................... 32

LXT380 JTAG Architecture ................................................................................. 37

JTAG State Diagram ........................................................................................... 39

Analog Test Port Application............................................................................... 45

Transmit Clock Timing ........................................................................................ 51

Receive Clock Timing Diagram........................................................................... 52

JTAG Timing ....................................................................................................... 52

Non-Multiplexed Intel Mode Read Timing ........................................................... 54

Multiplexed Intel Read Timing............................................................................. 54

Non-Multiplexed Intel Mode Write Timing ........................................................... 56

Multiplexed Intel Mode Write Timing ................................................................... 56

Non-Multiplexed Motorola Mode Read Timing.................................................... 58

Multiplexed Motorola Mode Read Timing............................................................ 59

Non-Multiplexed Motorola Mode Write Timing .................................................... 60

Multiplexed Motorola Mode Write Timing ............................................................ 61

Serial Input Timing .............................................................................................. 62

Serial Output Timing ........................................................................................... 62

E1 Mask Template .............................................................................................. 63

E1 Jitter Tolerance .............................................................................................. 64

LXT380 144 Pin LQFP Package Dimensions ..................................................... 66

LXT380 160 Pin PBGA Package Dimensions..................................................... 67

Tables

LXT380 Pin Description ...................................................................................... 11

Operation Mode Summary .................................................................................. 28

Operating Mode .................................................................................................. 29

Serial and Parallel Port Register Addresses ....................................................... 33

ID Register (00H) ................................................................................................ 34

Analog Loopback Register (01H) ........................................................................ 34

Remote Loopback Register (02H)....................................................................... 34

TAOS Enable Register (03H).............................................................................. 34

Datasheet

Octal E1 Line Interface Unit — LXT380

LOS Status Monitor Register (04H).....................................................................35

DFM Status Monitor Register (05H) ....................................................................35

LOS Interrupt Enable Register (06H) ..................................................................35

DFM Interrupt Enable Register (07H)..................................................................35

LOS Interrupt Status Register (08H) ...................................................................35

DFM Interrupt Status Register (09H)...................................................................35

Software Reset Register (0AH) ...........................................................................35

Performance Monitoring Register........................................................................36

Digital Loopback Register (0CH).........................................................................36

LOS Criteria Register (0DH)................................................................................36

Automatic TAOS Select Register (0EH)..............................................................36

TAP State Description .........................................................................................38

Boundary Scan Register, BSR ............................................................................40

Device Identification Register, IDR......................................................................43

Analog Port Scan Register, ASR.........................................................................44

Instruction Register, IR........................................................................................46

Absolute Maximum Ratings.................................................................................46

Recommended Operating Conditions .................................................................47

DC Characteristics ..............................................................................................47

Transmit Transmission Characteristics ...............................................................48

Receive Transmission Characteristics ................................................................49

Analog Test Port Characteristics.........................................................................50

Transmit Timing Characteristics..........................................................................50

Receive Timing Characteristics...........................................................................51

JTAG Timing Characteristics...............................................................................52

Intel Mode Read Timing Characteristics .............................................................53

Intel Mode Write Timing Characteristics..............................................................55

Motorola Bus Read Timing Characteristics .........................................................57

Motorola Mode Write Timing Characteristics ......................................................59

Serial I/O Timing Characteristics.........................................................................61

Transformer Specifications..................................................................................62

G.703 2.048 Mbit/s Pulse Mask Specifications ...................................................63

Datasheet

LXT380BE Related Products

	LXT380BE
Description	PCM Transceiver, 1-Func, PBGA160, PLASTIC, BGA-160
Maker	Cortina Systems Inc
Objectid	2146528235
Parts packaging code	BGA
package instruction	BGA,
Contacts	160
Reach Compliance Code	compliant
compound_id	6923421
JESD-30 code	S-PBGA-B160
length	15 mm
Number of functions	1
Number of terminals	160
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Certification status	Not Qualified
Maximum seat height	1.8 mm
Nominal supply voltage	3.3 V
surface mount	YES
Telecom integrated circuit types	PCM TRANSCEIVER
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	15 mm

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