Data Sheet
September 2001
L7585G Full-Feature, Low-Power SLIC and Switch
Features
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Description
The L7585G Full-Feature, Low-Power Subscriber Loop
Interface Circuit (SLIC) and Switch integrates the battery
feed, test access relay, and ringing relay that are necessary
to interface a codec to the tip and ring of a subscriber loop
into one low-power, low-cost package. It is built using a
90 V complementary bipolar (CBIC) process and a 320 V
Bipolar-CMOS-DMOS (BCDMOS) process. The device
is available in a 44-pin MQFP package.
The device can be connected directly to the Agere Systems
Inc. T8531/T8536 16-Channel Programmable Codec Chip
Set without the need for any ac interface components.
Low active power
Quiet tip/ring polarity reversal
Distortion-free on-hook transmission
35 V to 60 V power supply operation
14 operating states:
— Forward battery active
— Reverse battery active
— Ground start (3)
— Forward battery ring open
— Reverse battery ring open
— Reverse battery tip open
— High impedance
— Ringing (2)
— Low current (2)
— Disconnect
Self-test in all operating states
Independent, adjustable ac and dc parameters:
— Switchhook detector threshold
— Loop current limit
— dc feed resistance
— Termination impedance
Integrated ringing access relay
Integrated test-in relay
Integrated relay driver
Integrated ring trip detector
Thermal protection
44-pin, metric quad flat package (MQFP)
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L7585G Full-Feature, Low-Power SLIC and Switch
Data Sheet
September 2001
Table of Contents
Contents
Page
Figures
Page
Features.................................................................................1
Description ...........................................................................1
Architectural Diagram ..........................................................3
Pin Information.....................................................................4
Operating States....................................................................7
Forward Battery Active State ............................................7
Ground Start/Tip Open State .............................................7
Ground Start/Tip Ground State..........................................8
Forward Battery Ring Open State......................................8
Ringing States (2) ..............................................................8
Disconnect State ................................................................8
Forward Battery Low-Current Active State ......................8
High-Impedance State .......................................................8
Reverse Battery Active State .............................................8
Reverse Battery Tip Open State ........................................8
Ground Start/Tip Amplifier State ......................................9
Reverse Battery Ring Open State ......................................9
Reverse Battery Low-Current Active State .......................9
Absolute Maximum Ratings (T
A
= 25 °C) ...........................9
Electrical Characteristics ....................................................10
On-State Switch V-I Characteristics ..................................17
Applications........................................................................18
Tip/Ring Protection .........................................................18
NDET Under Fault Conditions........................................18
Power, Clocking, and Layout ..........................................18
Ring Trip..........................................................................19
False On-Hook Transients ...............................................19
Application Diagram ..........................................................20
Outline Diagram .................................................................21
44-Pin MQFP...................................................................21
Ordering Information .........................................................22
Figure 1. Architectural Diagram ......................................... 3
Figure 2. 44-Pin Diagram (MQFP) ..................................... 4
Figure 3. On-State Switch V-I Characteristics .................. 17
Figure 4. 16-Channel Line Card Solution ......................... 20
Tables
Page
Table 1. Pin Descriptions .................................................... 5
Table 2. B0—B3 Input State Coding ................................... 7
Table 3. B4—B5 Input State Coding ................................... 7
Table 4. Operating Conditions and Powering ................... 10
Table 5. Ring Trip Detector .............................................. 10
Table 6. Battery Feed Characteristics ............................... 11
Table 7. Analog Signal Pins .............................................. 12
Table 8. Transmission Characteristics .............................. 13
Table 9. Data Interface and Logic (Logic Inputs
[CLK, NCS, and B0—B5] and
Outputs [NDET]) ............................................... 14
Table 10. Timing Requirements (CLK, B0—B5,
and NCS) ......................................................... 14
Table 11. Relay Driver (RDO) .......................................... 14
Table 12. Ringing Return Access Switch (SW1) .............. 15
Table 13. Test-In Access Switches
(SW3 and SW6) ............................................... 15
Table 14. Tip and Ring Break Switches
(SW2 and SW4) ............................................... 16
Table 15. Tip and Ring Feedback Switches
(SW2a and SW4a) ........................................... 16
Table 16. Ringing Access Switch (SW5) .......................... 17
2
Data Sheet
September 2001
L7585G Full-Feature, Low-Power SLIC and Switch
Architectural Diagram
NCS B5 B4 B3 B2 B1 B0
AGND
V
CCA
ITR
VITR
100 kΩ
+5 A
CLK
NDET
PARALLEL DATA LATCH
AND LOGIC
NPDAT
NPDAR
–
REF
RD FB NRT
SW1—SW6
CONTROL
NLC
ITR/198
+5 A
50
µA
FB
SW1
45
Ω
TRNG
TTI
PT
SW3
45
Ω
SW2
25
Ω
V
BAT
ITR
TIP/RING
CURRENT
SENSE
ITR
RFR
20
Ω
AR
–
RTI
SW6
SW4a
DC
OUT
RSW
SW5
RRNG
GTO
RTS
RD
+5 A
RELAY
DRIVER
RING TRIP
DETECTOR
NRT
FB1
dc
FEEDBACK
AND
CURRENT
LIMIT
BUFFER
V
BAT
NPDAR
BUFFER
NPDAT
RFT
20
Ω
AT
+
ac
INTERFACE
+
BUFFER
–
ac
RCVN
RCVP
SW2a
4 kΩ
LCTH
IN
2.4 V
REFERENCE
DC
OUT
VRTX
+
AX
AAC
VTX
TXI
SWITCHHOOK
DETECTOR
+
–
RECTIFIER
GAIN = 3
OUT
SW4
PR
dc
BUFFER
FB2
+5 D
+10 V
75
µA
V
BAT
I
PROG
DCR
CF2 CF1
V
BAT
RDO
DGND
V
CCD
V
SP
V
BAT
BGND
12-3290.e(F)
Figure 1. Architectural Diagram
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L7585G Full-Feature, Low-Power SLIC and Switch
Data Sheet
September 2001
Pin Information
DC
OUT
AGND
RCVN
VRTX
35
RCVP
LCTH
I
PROG
V
CCA
DCR
44
CF1
FB2
FB1
BGND
V
BAT
V
BAT
V
SP
NCS
CLK
NDET
DGND
1
2
3
4
5
6
7
8
9
10
11
12
RDO
43
42
41
40
39
38
37
36
34
33
32
31
30
29
28
27
26
25
24
23
TXI
VITR
ITR
BGND
V
BAT
DGND
V
CCD
B0
B1
B2
B3
13
RTS
14
RSW
15
RRNG
16
PR
17
RTI
18
TTI
19
PT
20
TRNG
21
B5
22
B4
VTX
CF2
12-2571H (F)
Figure 2. 44-Pin Diagram (MQFP)
4
Data Sheet
September 2001
L7585G Full-Feature, Low-Power SLIC and Switch
Pin Information
(continued)
Table 1. Pin Descriptions
Pin
1
2
Symbol
CF1
FB2
Type
I/O
I
Name/Function
Filter Capacitor 1.
Connect a 0.22 µF, 100 V capacitor from this pin to pin CF2.
Forward Battery Slowdown 2.
A capacitor from FB1 to AGND and from FB2 to AGND will
ramp the polarity reversal transition when quiet polarity reversal is required. If not needed, the pin
can be left open.
Forward Battery Slowdown 1.
A capacitor from FB1 to AGND and from FB2 to AGND will
ramp the polarity reversal transition when quiet polarity reversal is required. If not needed, the pin
can be left open.
Battery Ground.
Ground return for the battery (V
BAT
) supply.
Battery Supply.
Negative high-voltage power supply.
Battery Supply.
Negative high-voltage power supply.
+10 V Supply.
+10 V bias supply for switch circuitry.
Not Channel Select.
A low-to-high transition on this logic input stores the data on pins B0—B5
into the input latches on the SLIC. When NCS is either high or low, the SLIC is unaffected by data
on pins B0—B5.
Clock.
Clock input.
Not Detect.
When low, this logic output indicates either a ring trip or an off-hook condition, de-
pending on the input state of the SLIC. If either the BCDMOS portion or CBIC portion of this de-
vice enters thermal shutdown, NDET will be forced low.
Digital Ground.
Ground return for V
CCD
and relay driver flyback current.
Relay Driver.
This output drives an external relay. RDO is low (relay operated) when a low input
on B5 is latched into the SLIC.
Ring Trip Sense.
Sense input for the ring trip detector.
Ring Lead Ringing Access Switch.
Ringing relay connects this pin to pin RRNG. Connect this
pin to pin PR through a 500
Ω
current-limiting resistor.
Ring Lead Ringing Supply.
Connect this pin to the ringing supply.
Protected Ring.
The output of the ring driver and input to the transmit current sense circuit. Con-
nect to the ring of the loop through overvoltage protection.
Ring Lead Test-In.
Test-in relay connects this pin to PR. Connect RTI to the ring lead of the
test-in bus.
Tip Lead Test-In.
Test-in relay connects this pin to PT. Connect TTI to the tip lead of the test-in
bus.
Protected Tip.
The output of the tip driver and input to the transmit current sense circuit. Connect
to the tip of the loop through overvoltage protection.
Tip Lead Ringing Supply.
Ringing relay connects this pin to PT. Connect TRNG to the ringing
supply return.
Bit 5.
B0—B5 determine the state of the SLIC. See Operating States.
3
FB1
I
4
5
6
7
8
BGND
V
BAT
V
BAT
V
SP
NCS
—
—
—
—
I
9
10
CLK
NDET
I
O
11
12
13
14
15
16
17
18
19
20
21
DGND
RDO
RTS
RSW
RRNG
PR
RTI
TTI
PT
TRNG
B5
—
O
I
O
I
I/O
I
I
I/O
O
I
Note: On the printed-wiring board (PWB), make the leads to BGND and V
BAT
as wide as possible for thermal and electrical reasons. Also, maximize the
amount of PWB copper on all leads connected to this device for the lowest operating temperature.
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51mcu
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