256MB, 512MB, 1GB Registered DIMM
DDR SDRAM
DDR SDRAM Registered Module
184pin Registered Module based on 256Mb E-die
with 72-bit ECC
66 TSOP-II and 60 ball FBGA
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.0 July 2005
256MB, 512MB, 1GB Registered DIMM
Table of Contents
DDR SDRAM
1.0 Ordering Information................................................................................................................... 4
2.0 Operating Frequencies................................................................................................................ 4
3.0 Feature.......................................................................................................................................... 4
4.0 Pin Configuration (Front side/back side) ................................................................................. 5
5.0 Pin Description ............................................................................................................................ 5
6.0 Functional Block Diagram .......................................................................................................... 6
6.1 256MB, 32M x 72 ECC Module (M312L3223ET(U)S)
........................................................................... 6
6.2 512MB, 64M x 72 ECC Module (M312L6423ET(U)S)
.......................................................................... 7
6.3 512MB, 64M x 72 ECC Module (M312L6420ET(U)S)
.......................................................................... 8
6.4 1GB, 128M x 72 ECC Module (M312L2828ET(U)0)
............................................................................ 9
6.5 256MB, 32M x 72 ECC Module (M312L3223EG(Z)0).......................................................................................
10
6.6 512MB, 64M x 72 ECC Module (M312L6423EG(Z)0)
........................................................................ 11
6.7 512MB, 64M x 72 ECC Module (M312L6420EG(Z)0).......................................................................................
12
6.8 1GB, 128M x 72 ECC Module (M312L2820EG(Z)0) .........................................................................................
13
7.0 Absolute Maximum Ratings...................................................................................................... 14
8.0 Power & DC Operating Conditions (SSTL_2 In/Out) .............................................................. 14
9.0 DDR SDRAM IDD spec table ..................................................................................................... 15
9.1 M312L3223ET(U)S [ (32M x 8) * 9 , 256MB Module ]
........................................................................ 15
9.2 M312L6423ET(U)S [ (32M x 8) * 18 , 512MB Module ]
....................................................................... 15
9.3 M312L6420ET(U)S [ (64M x 4) * 18 , 512MB Module ] .....................................................................................
16
9.4 M312L2828ET(U)0 [ (st.128M x 4) * 18 , 1GB Module ]
..................................................................... 16
9.5 M312L3223EG(Z)0 [ (32M x 8) * 9 , 256MB Module ].......................................................................................
17
9.6 M312L6423EG(Z)0 [ (32M x 8) * 18 , 512MB Module ]
...................................................................... 17
9.7 M312L6420EG(Z)0 [ (64M x 4) * 18 , 512MB Module ]
....................................................................... 18
9.8 M312L2820EG(Z)0 [ (64M x 4) * 36, 1GB Module ]
........................................................................... 18
10.0 AC Operating Conditions........................................................................................................ 19
11.0 Input/Output Capacitance ....................................................................................................... 19
12.0 AC Timming Parameters & Specifications ............................................................................ 20
13.0 System Characteristics for DDR SDRAM .............................................................................. 21
14.0 Component Notes.................................................................................................................... 22
15.0 System Notes ........................................................................................................................... 23
16.0 Command Truth Table............................................................................................................. 24
17.0 Physical Dimensions............................................................................................................... 25
17.1 32M x 72 (M312L3223ET(U)S)
.................................................................................................... 25
17.2 64M x 72 (M312L6423ET(U)S), (M312L6420ET(U)S)
...................................................................... 26
17.3 st.128M x 72 (M312L2828ET(U)0)
............................................................................................... 27
17.4 32M x 72 (M312L3223EG(Z)0)
.................................................................................................... 28
17.5 64M x 72 (M312L6423EG(Z)0), (M312L6420EG(Z)0)
....................................................................... 29
17.6 128M x 72 (M312L2820EG(Z)0)
................................................................................................... 30
Rev. 1.0 July 2005
256MB, 512MB, 1GB Registered DIMM
Revision History
Revision
1.0
Month
July
Year
2005
History
- Merged TSOP and FBGA based RDIMM, Deleted 1.7” Height DIMM
DDR SDRAM
Rev. 1.0 July 2005
256MB, 512MB, 1GB Registered DIMM
DDR SDRAM
184Pin Registered DIMM based on 256Mb E-die (x4, x8)
1.0 Ordering Information
Part Number
M312L3223ET(U)S-CA2/B0
M312L6423ET(U)S-CA2/B0
M312L6420ET(U)S-CA2/B0
M312L2828ET(U)0-CA2/B0
M312L3223EG(Z)0-CCC/B3
M312L6423EG(Z)0-CCC/B3
M312L6420EG(Z)0-CCC/B3
M312L2820EG(Z)0-CCC/B3
Density
256MB
512MB
512MB
1GB
256MB
512MB
512MB
1GB
Organization
32M x 72
64M x 72
64M x 72
128M x 72
32Mx72
64M x 72
64M x 72
128M x 72
Component Composition
32Mx8( K4H560838E) * 9EA
32Mx8( K4H560838E) * 18EA
64Mx4( K4H560438E) * 18EA
st.128Mx4( K4H510638E) * 18EA
32Mx8( K4H560838E) * 9EA
32Mx8( K4H560838E) * 18EA
64Mx4( K4H560438E) * 18EA
64Mx4( K4H560438E) * 36EA
Height
1,200mil
1,200mil
1,200mil
1,200mil
1,125mil
1,125mil
1,125mil
1,200mil
Note : Leaded and Lead-free(Pb-free) can be discriminated by PKG P/N
(T : 66 TSOP with Leaded, U : 66 TSOP with Lead-free)
(G : 60 FBGA with Leaded, Z : 60 FBGA with Lead-free)
2.0 Operating Frequencies
CC(DDR400@CL=3)
Speed @CL2
Speed @CL2.5
Speed @CL3
CL-tRCD-tRP
-
166MHz
200MHz
3-3-3
B3(DDR333@CL=2.5)
133MHz
166MHz
-
2.5-3-3
A2(DDR266@CL=2)
133MHz
133MHz
-
2-3-3
B0(DDR266@CL=2.5)
100MHz
133MHz
-
2.5-3-3
3.0 Feature
• VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333
• VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe [DQ] (x4,x8) & [L(U)DQS] (x16)
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency : DDR266(2, 2.5 Clock), DDR333(2.5 Clock), DDR400(3 Clock)
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
• Serial presence detect with EEPROM
• SSTL_2 Interface
• 66pin TSOP II and 60 ball FBGA
Leaded & Pb-Free(RoHS compliant)
package
Rev. 1.0 July 2005
256MB, 512MB, 1GB Registered DIMM
4.0 Pin Configuration (Front side/back side)
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Front
VREF
DQ0
VSS
DQ1
DQS0
DQ2
VDD
DQ3
NC
RESET
VSS
DQ8
DQ9
DQS1
VDDQ
*CK1
*CK1
VSS
DQ10
DQ11
CKE0
VDDQ
DQ16
DQ17
DQS2
VSS
A9
DQ18
A7
VDDQ
DQ19
Pin
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
Front
A5
DQ24
VSS
DQ25
DQS3
A4
VDD
DQ26
DQ27
A2
VSS
A1
CB0
CB1
VDD
DQS8
A0
CB2
VSS
CB3
BA1
KEY
DQ32
VDDQ
DQ33
DQS4
DQ34
VSS
BA0
DQ35
DQ40
Pin
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
Front
VDDQ
WE
DQ41
CAS
VSS
DQS5
DQ42
DQ43
VDD
*CS2
DQ48
DQ49
VSS
*CK2
*CK2
VDDQ
DQS6
DQ50
DQ51
VSS
VDDID
DQ56
DQ57
VDD
DQS7
DQ58
DQ59
VSS
NC
SDA
SCL
Pin
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
Back
VSS
DQ4
DQ5
VDDQ
DM0/DQS9
DQ6
DQ7
VSS
NC
NC
NC
VDDQ
DQ12
DQ13
DM1/DQS10
VDD
DQ14
DQ15
CKE1
VDDQ
*BA2
DQ20
A12
VSS
DQ21
A11
DM2/DQS11
VDD
DQ22
A8
DQ23
Pin
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
DDR SDRAM
Back
VSS
A6
DQ28
DQ29
VDDQ
DM3/DQS12
A3
DQ30
VSS
DQ31
CB4
CB5
VDDQ
CK0
CK0
VSS
DM8/DQS17
A10
CB6
VDDQ
CB7
KEY
VSS
DQ36
DQ37
VDD
DM4/DQS13
DQ38
DQ39
VSS
DQ44
Pin
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
Back
RAS
DQ45
VDDQ
CS0
CS1
DM5/DQS14
VSS
DQ46
DQ47
*CS3
VDDQ
DQ52
DQ53
*A13
VDD
DM6/DQS15
DQ54
DQ55
VDDQ
NC
DQ60
DQ61
VSS
DM7/DQS16
DQ62
DQ63
VDDQ
SA0
SA1
SA2
VDDSPD
Note :
1. * : These pins are not used in this module.
2. Pins 111, 158 are NC for 1row module & used for 2row module.
3. Pins 97, 107, 119, 129, 140, 149, 159, 169, 177 : DM (x8 base module) or DQS (x4 base module).
5.0 Pin Description
Pin Name
A0 ~ A12
BA0 ~ BA1A
DQ0 ~ DQ63
DQS0 ~ DQS17
CK0,CK0 ~ CK2, CK2
CKE0, CKE1(for double banks)
CS0, CS1(for double banks)
RAS
CAS
WE
CB0 ~ CB7
Function
Address input (Multiplexed)
Bank Select Address
Data input/output
Data Strobe input/output
Clock input
Clock enable input
Chip select input
Row address strobe
Column address strobe
Write enable
Check bit(Data-in/data-out)
Pin Name
DM0 ~ DM8
VDD
VDDQ
VSS
VREF
VDDSPD
SDA
SCL
SA0 ~ 2
VDDID
NC
Data - in mask
Power supply
(2.5V for DDR266/333, 2.6V for DDR400)
Power Supply for DQS
(2.5V for DDR266/333, 2.6V for DDR400)
Ground
Power supply for reference
Serial EEPROM Power/Supply ( 2.3V to 3.6V )
Serial data I/O
Serial clock
Address in EEPROM
VDD, VDDQ level detection
No connection
Function
Note : VDDID defines relationship of VDD and VDDQ, and the default status of it is open (VDD=VDDQ)
Rev. 1.0 July 2005
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