Integrated
Circuit
Systems, Inc.
ICS950220
Programmable Timing Control Hub™ for P4™
Recommended Application:
CK-408 clock for Intel
®
845 chipset.
Output Features:
•
3 - Pairs of differential CPU clocks @ 3.3V
•
3 - 3V66 @ 3.3V
•
9 - PCI @ 3.3V
•
2 - 48MHz @ 3.3V fixed
•
1 - 24_48MHz @ 3.3V, 48MHz, 24Mhz or 66MHz
•
1 - REF @ 3.3V, 14.318MHz
Features/Benefits:
•
Programmable output frequency.
•
Programmable output divider ratios.
•
Programmable output rise/fall time.
•
Programmable output skew.
•
Programmable spread percentage for EMI control.
•
Watchdog timer technology to reset system
if system malfunctions.
•
Programmable watch dog safe frequency.
•
Support I
2
C Index read/write and block read/write
operations.
•
Uses external 14.318MHz crystal.
Key Specifications:
•
CPU Output Jitter <150ps
•
3V66 Output Jitter <250ps
•
CPU Output Skew <100ps
Pin Configuration
VDDREF
X1
X2
GND
1
*FS0/PCICLK7
1
**FS1/PCICLK8
VDDPCI
GND
1
*WDEN/PCICLK0
PCICLK1
PCICLK2
PCICLK3
VDDPCI
GND
PCICLK4
PCICLK5
PCICLK6
VDD3V66
GND
3V66_1
3V66_2
3V66_3
#RESET
VDDA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
REF/FS2**
CPUCLKT0
CPUCLKC0
VDDCPU
CPUCLKT1
CPUCLKC1
GND
VDDCPU
CPUCLKT2
CPUCLKC2
MULTISEL0*
I REF
GND
48MHz_USB/FS3**
48MHz_DOT/SEL_24_48*
AVDD48
GND
3V66_0/24_48MHZ#/FS4**
VDD3V66
GND
SCLK
SDATA
Vtt_PWRGD/PD#*
GND
1
48-Pin 300-mil SSOP
1. These outputs have 2X drive strength.
* Internal Pull-up resistor of 120K to VDD
** these inputs have 120K internal pull-down
to GND
Block Diagram
PLL2
/2
Frequency Table
48MHz_USB
48MHz_DOT
ICS950220
FS4 FS3 FS2 FS1 FS0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
0
1
CPUCLK
MHz
100.00
133.33
66.67
200.00
3V66
MHz
66.67
66.67
66.67
66.67
PCICLK
MHz
33.33
33.33
33.34
33.33
X1
X2
XTAL
OSC
3V66
DIVDER
3
3V66 (3:1)
3V66_0/24_48MHZ#
PLL1
Spread
Spectrum
CPU
DIVDER
3
3
REF
CPUCLKT (2:0)
CPUCLKC (2:0)
PCICLK (6:0)
Reset#
For additional frequency selections please refer to Byte 0.
SEL24_48
WDEN
MULTSEL0
FS (4:0)
SDATA
SCLK
Vtt_PWRGD#
PD#
Control
Logic
PCI
DIVDER
Power Groups
VDDA = Analog Core PLL
VDDREF = REF, Xtal
AVDD48 = 48MHz
7
Config.
Reg.
I REF
0467F—07/28/05
Integrated
Circuit
Systems, Inc.
ICS950220
General Description
The
ICS950220
is a single chip clock solution for desktop designs using the Intel 845 chipset with PC133 or DDR memory. It
provides all necessary clock signals for such a system.
The
ICS950220
is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). This part
incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a
serially programmable I
2
C interface, this device can adjust the output clocks by configuring the frequency setting, the output
divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. M/N control can configure output frequency with resolution up to 0.1MHz increment.
Pin Description
PIN NUMBER
1, 7, 13, 18,
30, 41, 45
2
3
4, 8, 14, 19, 25, 29,
32, 36, 42
22, 21, 20
5
VDD
X1
X2
GND
3V66 (3:1)
PCICLK7
FS0
PCICLK8
6
FS1
9
WDEN
PCICLK0
IN
IN
OUT
OUT
OUT
PWR
IN
IN
IN
I/O
OUT
IN
PWR
OUT
IN
IN
OUT
OUT
IN
OUT
OUT
IN
OUT
L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n .
Hardware enable of watch dog circuit. Enabled when latched high.
3.3V PCI clock output.
3.3V PCI clock outputs.
Real time system reset signal for frequency value or watchdog timmer timeout.
This signal is active low.
Analog power 3.3V.
This 3.3V LVTTL input is a level sensitive strobe used to determine when FS (4:0)
inputs are valid and are ready to be sampled (active high).
Asynchronous active low input pin used to power down the device into a low
power state. The inter nal clocks are disabled and the VCO and the cr ystal are
s t o p p e d . T h e l a t e n c y o f t h e p ow e r d ow n w i l l n o t b e g r e a t e r t h a n 3 m s.
Clock pin for I
2
C circuitr y 5V tolerant.
Data pin for I
2
C circuitr y 5V tolerant.
3.3V output selectable through I
2
C to be 66MHz from internal VCO or
48MHz/24MHz.
L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n .
Analog power 3.3V.
3.3V Fixed 48MHz clock output for DOT.
This selects the frequency for the SEL24_48 output.
H i g h = 2 4 M H z , L ow = 4 8 M H z .
L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n .
3.3V Fixed 48MHz clock output for USB.
This pin establishes the reference current for the CPUCLK pairs. This pin requires
a fixed precision resistor tied to ground in order to establish the appropriate
current.
3.3V LVTTL input for selecting the current multiplier for CPU outputs
"Complementor y" clocks of differential pair CPU outputs. These are current
outputs and external resistors are required for voltage bias.
"True" clocks of differential pair CPU outputs. These are current outputs and
external resistors are required for voltage bias.
L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n .
3.3V, 14.318MHz reference clock output.
PIN NAME
TYPE
PWR
IN
OUT
PWR
OUT
OUT
IN
OUT
3.3V power supply.
Cr ystal input, has inter nal load cap (33pF) and feedback resistor from X2.
Cr ystal output, nominally 14.318MHz. Has inter nal load cap (33pF).
Ground pins for 3.3V supply.
3.3V Fixed 66MHz clock outputs for HUB.
3.3V PCI clock output
L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n .
3.3V PCI clock output.
DESCRIPTION
17, 16, 15, 12, 11, 10 PCICLK (6:1)
23
24
RESET#
VDDA
Vtt_PWRGD
26
PD#
28
27
31
33
34
35
37
38
39, 43, 46
40, 44, 47
48
0467F—07/28/05
SCLK
SDATA
3V66_0/24_48MHZ#
FS4
AVDD48
48MHz_DOT
SEL24_48
FS3
48MHz_USB
I REF
MULTSEL0
CPUCLKC (2:0)
CPUCLKT (2:0)
FS2
REF
2
Integrated
Circuit
Systems, Inc.
ICS950220
General SMBus serial interface information
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte location = N
ICS clock will
acknowledge
Controller (host) sends the data byte count = X
ICS clock will
acknowledge
Controller (host) starts sending
Byte N through
Byte N + X -1
• ICS clock will
acknowledge
each byte
one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
How to Read:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) will send start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will
acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3
(H)
ICS clock will
acknowledge
ICS clock will send the data byte count = X
ICS clock sends
Byte N + X -1
ICS clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8)
.
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host)
starT bit
T
Slave Address D2
(H)
WR
WRite
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ICS (Slave/Receiver)
Index Block Read Operation
Controller (Host)
T
starT bit
Slave Address D2
(H)
WR
WRite
Beginning Byte = N
ACK
RT
Repeat starT
Slave Address D3
(H)
RD
ReaD
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ICS (Slave/Receiver)
ACK
ACK
Byte N + X - 1
ACK
P
stoP bit
Byte N + X - 1
N
P
Not acknowledge
stoP bit
0467F—07/28/05
4
Embedded System
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EEWORLD
