S1C33E07
CMOS 32-bit Application Specific Controller
32-bit RISC CPU-Core Optimized for SoC (EPSON S1C33 PE)
Built-in 8KB RAM
SDRAM Controller with Burst Control
Generic DMA Controller (HSDMA/IDMA)
6-ch. PWM Control Timer/Counter
Supports Several Interfaces
SIO with FIFO (IrDA1.0), SPI, I2S and DCSIO
●
5-ch. ADC for Analog Input
●
Built-in LCD Controller with 12KB IVRAM
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DESCRIPTIONS
The S1C33E07 is a high cost performance 32-bit RISC controller for specific applications that require a lot of
general-purpose I/O, a powerful PWM Timer/Counter function, several serial interfaces including USB-FS device
controller, an ADC and a LCD display system, such as middle-low range electronic dictionaries and label writers/printers.
The S1C33E07 consists of a 32-bit RISC CPU-Core, generic DMA controller, USB-FS device controller, PWM control
Timer/Counter, several interfaces (SIO including IrDA1.0, SPI, I2S and DCSIO), ADC, RAM/Shared IVRAM and RTC
implemented by EPSON SoC design technology using 0.18
μm
Mixed Analog Low CMOS Process.
FEATURES
●Technology
・
0.18
μm
AL-4-Layers mixed analog low power CMOS process technology
●CPU
・
・
・
・
・
・
EPSON original C33 PE 32-bit RISC CPU-Core with AMBA bus optimized for SoC
Max. 60 MHz operation
Internal 2-stage pipeline and 4 instruction queues
Instruction set: 128 instructions (16-bit fixed length)
Basic instructions are compatible with the S1C33 32-bit RISC Cores.
Dual AMBA bus system for CPU and LCDC
●Internal
Memories
・
8KB RAM
・
12KB IVRAM (used as general-purpose RAM or VRAM)
・
2KB DST RAM (used as general-purpose RAM or IDMA descriptor table RAM)
●Oscillator
Circuit / PLL
OSC3 Oscillator Circuit
・
Crystal oscillation: 5 MHz min. to 48 MHz max.
・
Ceramic oscillation: 5 MHz min. to 48 MHz max.
・
External clock input: 5 MHz min. to 48 MHz max.
PLL
・
PLL input frequency: 5 MHz min. to 50 MHz max.
・
PLL output frequency: 25 MHz min. to 90 MHz max.
・
Multiplication rate:
⋅1
~
⋅15.
OSC1 Oscillator Circuit
・
Crystal oscillation/External clock input: 32.768 kHz typ.
●High
Speed Bus (HB) Modules
SRAMC (SRAM Controller)
・
25-bit address lines and 8/16-bit selectable data bus
・
UP to a 512M-byte (A[24:0]) address space is provided for each chip enable signal.
・
Max. 8 chip enable signals are available to connect external devices.
・
Programmable bus wait cycle (0 to 7 cycles)
・
Supports external wait signals.
S1C33E07
・
4GB physical address space is available.
-
The physical address space is divided into 23 areas: Area 0 to Area 22.
- Areas 0 to 4 and Area 6 are system reserved.
・
Supports only Little-Endian access to each area.
・
Memory mapped I/O
・
Supports both A0 and BS (Bus Strobe) access type external devices
・
SRAM, ROM, and Flash ROM direct access interfaces are built in.
SDRAMC (SDRAM Controller with SDRAM APP and AHB Local Bus Arbiter)
・
Supports SDRAM direct interface.
・
Supports only SDRAM devices with 16-bit data bus.
Minimum configuration: 16M bits (2MB), 16-bit SDRAM
⋅
1
Maximum configuration: 512M bits (64MB), 16-bit SDRAM
⋅
1
・
CAS latency: 1, 2, or 3 programmable
・
Supports burst and single read/write.
・
Supports DQM (byte write) function.
・
Supports max. 4 SDRAM banks and bank active mode.
・
Incorporates a 12-bit auto-refresh counter.
・
Intelligent self-refresh function for low power operation
・
2-stage
⋅
32-bit data buffer and 8-stage
⋅
32-bit
⋅
2-slot instruction buffer built-in
・
Supports up to max. 90 MHz SDRAM clock.
- When the CPU clock is 48 MHz, the SDRAM clock can be set to max. 48 MHz.
- When the CPU clock is 45 MHz, the SDRAM clock can be set to max. 90 MHz using the PLL.
・
Arbitrates ownership of the external bus between the CPU, DMAC, LCDC and SRAMC.
DMAC (Direct Memory Access Controller)
・
4-ch. high speed hardware DMA
・
128-ch. intelligent DMA (variable data transfer controller) with specific control table
IVRAMARB (Internal Video RAM Arbiter)
・
Contains a 12KB SRAM (3,072 words
⋅
16 bits
⋅
2).
・
Arbitrates accesses from the LCDC and CPU.
・
Allows the CPU and LCDC to access IVRAM in minimum 2 cycles by 32-bit access.
・
Supports UMA (Unified Memory Access) for display
・
IVRAM is configurable as a 12KB general-purpose RAM in Area 0 using a control register if it is not
used as a video RAM.
●Peripheral
Bus (SAPB) Modules
TCU (Timer/Counter Unit with PWM Outputs)
・
6-ch. 16-bit timer/counter
・
Supports PWM outputs with DA16 (Digital D/A) mode.
・
Contains a prescaler, which can divide the peripheral clock by 1 to 4096, to generate the operating clock for
each channel.
・
Possible to invoke DMA transfer.
WDT (Watchdog Timer)
・
30-bit watchdog timer to generate an NMI interrupt
・
The watchdog timer overflow cycle (NMI interrupt cycle) is programmable.
・
The watchdog timer overflow signal can be output outside the IC.
ADC (A/D Converter)
・
5-ch. 10-bit A/D converter
・
Upper/lower limit interrupt is available.
・
Each ADC channel includes a data buffer.
・
Contains a prescaler, which can divide the peripheral clock by 2 to 256, to generate the operating
clock for ADC.
ITC (Interrupt Controller)
・
Possible to invoke DMA transfer
・
DMAC interrupt: 5 types
・
Input interrupt: 18 types
・
TCU interrupt: 12 types
・
EFSIO interrupt: 9 types
・
ADC interrupt: 2 types
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S1C33E07
RTC interrupt: 1 type
SPI interrupt: 3 types
DCSIO interrupt: 1 type
USB interrupt: 2 types
I2S interrupt: 1 type
LCDC interrupt: 1 type
GPIO (General-Purpose I/O Ports)
・
Max. 82 ports in the QFP24-144pin model.
* The S1C33E07 GPIO ports are shared with other peripheral function pins (EFSIO, PWM etc.).
Therefore, thenumber of GPIO ports depends on the peripheral functions used.
USB (Universal Serial Bus 2.0 compliant Full-Speed Device Controller)
・
Supports USB2.0 full speed (12M bps) mode.
・
Supports auto negotiation function.
・
Supports control, bulk, isochronous and interrupt transfers.
・
Supports 4-bulk end points and end point 0 (control).
・
Embedded 1K-byte programmable FIFO
・
Supports 8-bit local bus DMA port.
・
Possible to invoke DMA transfer.
・
Supports Async. DMA transfer.
・
Supports DMA slave mode.
・
Fixed 48 MHz clock for USB-FS.
・
Supports snooze mode.
RTC (Real Time Clock)
・
Contains time counters (seconds, minutes, and hours) and calendar counters (days, days of the
week, months, and year).
・
BCD data can be read from and written to both counters.
・
Capable of controlling the starting and stopping of time clocks.
・
A 30-second correction function can be implemented in software.
・
Periodic interrupts are possible.
CARD (Serial Input/Output with Direction Control)
・
Provides SmartMedia I/F signals (#SMRE, #SMWE).
・
Provides 8- or 16-bit NAND Flash I/F signals.
・
ECC function is available when reading/writing from/to NAND Flash type devices.
・
Supports NAND Flash booting function.
・
Supports EPSON middleware FS33.
EFSIO (Extended Serial Interface with FIFO Buffer)
・
3-ch. clock sync./async. serial interface
・
Contains FIFO data buffers (4 receive data buffer and 2 transmit data buffer are available for each
channel)
・
Contains a baud-rate generator (12-bit programmable timer).
・
Ch.1 only supports ISO7816 mode.
- Alternative MSB or LSB
- Memory card interface compatible with ISO7816-3 T=0 & T=1 protocol
- Programmable baud-rate and guard-time generation
- ISO7816 acknowledge and automatically repeat transmission
・
Possible to invoke DMA transfer.
SPI (Serial Peripheral Interface)
・
1 ch. SPI that operates in either master or slave mode
・
Supports 1- to 32-bit data transfer.
・
Data transfer timing (clock phase and polarity variations) is selectable from among 4 types.
・
A 1 to 65,536 clocks of delay can be inserted between transfers.
・
Generates transmit data register empty and receive data register full interrupts.
・
Supports both MMC and SD-card capabilities.
・
Possible to invoke DMA transfer.
DCSIO (Direction Control Serial Input/Output Port)
・
2-ch. input/output ports with a serial shifter
・
Input/output level detection to drive a state machine
・
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・
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・
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S1C33E07
・
1-wire or 2-wire communication protocol is simulated with software.
EGPIO (Extended GPIO)
・
Max. 17 configurable GPIO ports are available in addition to the standard GPIO ports. In die form,
Max. 91 ports are available.
* The EGPIO ports are shared with other peripheral function pins. Therefore, the number of EGPIO
ports depends on the peripheral functions used.
・
Most ports have a pull-up resistor that can be enabled/disabled with the control register.
・
Possible to drive the ports low.
CMU (Extended Clock Management Unit)
・
Controls clock supply to each peripheral block (static).
・
Manages reset and NMI inputs.
・
Switches the system clock source (MCLK, SDRAMCLK, or RTCCLK).
・
Controls the MCLK and RTCCLK oscillator circuits.
・
Turns on/off and controls frequency multiplication rate of the PLL.
・
Controls clocks according to the standby mode (SLEEP and HALT).
・
Controls divide ratios of the LCDC clock.
・
Manages the external bus clock.
MISC (Misc. Setting Register)
・
USB/RTC wait configuration registers
・
Debug port function select register
・
Boot mode configuration register
2
I S (Inter-IC Sound Bus Interface)
・
Supports universal audio I2S Bus Interface.
・
Operates as the master to generate the bit clock, word-select signal, data and master clock.
・
Generates the I2S interrupt signal.
・
Possible to invoke DMA transfer.
LCDC (STN/TFT LCD Controller with AMBA Bus)
VRAM:
・
Built-in a 12KB RAM usable as a display buffer or general-purpose RAM (register selectable)
・
Supports the UMA method allowing LCDC to access SDRAM (external VRAM) or IVRAM (internal
VRAM).
・
The external VRAM map (SDRAM) is configurable.
・
The sub window area can be located in IVRAM or external VRAM regardless of whether it contains
the main window area or not.
Display Support:
・
Supports single panel, single drive passive display.
・
4/8-bit monochrome LCD interface
・
4/8-bit color LCD interface
・
Direct support for 12-bit Generic HR-TFT interface
・
Picture-in-Picture Plus
・
The LCD panel width must be a multiple of 16 ÷ bits per pixel.
Display Modes:
・
Due to frame rate modulation, grayscale display is possible in up to 16 shades of gray when a
monochrome passive LCD panel is used.
Two-shade display in 1-bpp mode, Four-shade display in 2-bpp mode, 16-shade display in 4-bpp
mode
・
A maximum of 64K colors can be simultaneously displayed on a color passive LCD panel.
256-color display in 8-bpp mode, 4K-color display in 12-bpp mode, 64K-color display in 16-bpp
mode
・
A maximum of 4096 colors can be simultaneously displayed on a TFT panel.
Two-color display in 1-bpp mode, Four-color display in 2-bpp mode, 16-color display in 4-bpp
mode,
256-color display in 8-bpp mode, 4K-color display in 12-bpp mode
・
The look up table can be bypassed.
・
Max resolution: 320 × 240 pixels with 1 bpp black and white display (when IVRAM is used)
Display Features:
・
Picture in Picture (PIP)
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S1C33E07
Picture-in-Picture enables a secondary window (or sub-window) within the main display window.
The sub-window may be positioned anywhere within the virtual display and is controlled through
registers. The sub-window retains the same color depth as the main window. The speed of
generating a sub-window by hardware is faster than software. By using this PIP function, it can
greatly speed the GUI performance and CPU can have more performance to assign other
processing. (e.g. Voice etc.)
・
12-bit Generic HR-TFT I/F
The 12-bit Generic HR-TFT interface can support 320 × 240 Sharp HR-TFT Panel, SII TFT panel or
some other TFT panels. Because the timing of FPFRAM, FPLINE, and TFT_CTL0–3 are not fixed
for TFT panels, they can be controlled by register setting. By different register settings, you can get
your specified TFT I/F signal timing.
・
Clock Source
The LCDC clock can be internally divided 48 MHz by 1, 2, •••, 16. The clock division register is
located in CMU part.
●Operating
Voltage
・
V
DD
(Core): 1.70 to 1.90 V (Typ. 1.8 V) when a ceramic resonator is used for the USB clock
・
V
DD
(Core): 1.65 to 1.95 V (Typ. 1.8 V) when a crystal is used or an external clock is input
・
PLV
DD
: 1.65 to 1.95 V (Typ. 1.8 V)
・
V
DDH
(I/O): 2.70 to 3.60 V when the USB is not used (5-V tolerant I/O not supported)
・
V
DDH
(I/O): 3.00 to 3.60 V (Typ. 3.3 V) when the USB is used (5-V tolerant I/O not supported)
●Operating
Frequency
・
CPU: 60 MHz max.
・
USB: 48 MHz max.
・
SDRAMC: 90 MHz max.
・
LCDC: 60 MHz max.
・
Other peripheral circuits: 60 MHz max.
●Operating
Temperatures
・
-40 to 85°C (0 to 75°C when a ceramic resonator is used for the USB clock)
●Power
Consumption
・
During SLEEP: 1.0
μA
typ. (operation clock = 48 MHz)
・
During HALT: 3.0 mA typ. (operation clock = 48 MHz)
・
During execution:
Core
19.0 mA typ. (operation clock = 48 MHz)
SRAMC
3.4 mA typ. (operation clock = 48 MHz, idle state with the clock supplied)
SDRAMC
5.4 mA typ. (operation clock = 48 MHz, idle state with the clock supplied)
DMA
3.9 mA typ. (operation clock = 48 MHz, idle state with the clock supplied)
LCDC
5.3 mA typ. (operation clock = 48 MHz, idle state with the clock supplied)
USB
10.0 mA typ. (operation clock = 48 MHz, idle state with the clock supplied)
ADC
260.0
μA
typ. (idle state when ADC is enabled)
* By controlling the CPU clock through the Clock-Gear (CMU), current consumption can be reduced.
●Shipping
Form
・
Package: TQFP24-144pin (16 mm × 16 mm × 1.0 mm and 0.4 mm pin pitch)
PFBGA-180pin (12 mm × 12 mm × 1.2 mm and 0.8 mm ball pitch)
・
Die form: 168 pads with pad pitch 90
μm
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