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JANSR2N7261

Description
Power Field-Effect Transistor, 8A I(D), 100V, 0.35ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-205AF, MODIFIED TO-39, 3 PIN
CategoryDiscrete semiconductor    The transistor   
File Size282KB,5 Pages
ManufacturerMicrosemi
Websitehttps://www.microsemi.com
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JANSR2N7261 Overview

Power Field-Effect Transistor, 8A I(D), 100V, 0.35ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-205AF, MODIFIED TO-39, 3 PIN

JANSR2N7261 Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
Objectid1713985555
Parts packaging codeBCY
package instructionCYLINDRICAL, O-MBCY-W3
Contacts2
Reach Compliance Codecompliant
ECCN codeEAR99
Shell connectionDRAIN
ConfigurationSINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage100 V
Maximum drain current (ID)8 A
Maximum drain-source on-resistance0.35 Ω
FET technologyMETAL-OXIDE SEMICONDUCTOR
JEDEC-95 codeTO-205AF
JESD-30 codeO-MBCY-W3
JESD-609 codee0
Number of components1
Number of terminals3
Operating modeENHANCEMENT MODE
Package body materialMETAL
Package shapeROUND
Package formCYLINDRICAL
Polarity/channel typeN-CHANNEL
Certification statusQualified
GuidelineMIL-19500/601
surface mountNO
Terminal surfaceTIN LEAD
Terminal formWIRE
Terminal locationBOTTOM
Transistor component materialsSILICON
TECHNICAL DATA SHEET
6 Lake Street, Lawrence, MA 01841
1-800-446-1158 / (978) 620-2600 / Fax: (978) 689-0803
Website: http: //www.microsemi.com
RADIATION HARDENED N-CHANNEL MOSFET
Reference MIL-PRF-19500/601
DEVICES
LEVELS
2N7261
2N7261U
JANSR (100K RAD(Si))
JANSF (300K RAD(Si))
ABSOLUTE MAXIMUM RATINGS (T
C
= +25°C unless otherwise noted)
Parameters / Test Conditions
Drain – Source Voltage
Gate – Source Voltage
Continuous Drain Current
T
C
= +25°C
Continuous Drain Current
T
C
= +100°C
Max. Power Dissipation
Drain to Source On State Resistance
Operating & Storage Temperature
Note:
(1) Derated Linearly by 0.2 W/°C for T
C
> +25°C
(2) V
GS
= 12Vdc, I
D
= 5.0A
PRE-IRRADIATION ELECTRICAL CHARACTERISTICS
(T
A
= +25°C, unless otherwise
noted)
Parameters / Test Conditions
Drain-Source Breakdown Voltage
V
GS
= 0V, I
D
= 1mAdc
Gate-Source Voltage (Threshold)
V
DS
V
GS
, I
D
= 1.0mA
V
DS
V
GS
, I
D
= 1.0mA, T
j
= +125°C
V
DS
V
GS
, I
D
= 1.0mA, T
j
= -55°C
Gate Current
V
GS
= ±20V, V
DS
= 0V
V
GS
= ±20V, V
DS
= 0V, T
j
= +125°C
Drain Current
V
GS
= 0V, V
DS
= 80V
V
GS
= 0V, V
DS
= 100V, T
j
= +125°C
V
GS
= 0V, V
DS
= 80V, T
j
= +125°C
Static Drain-Source On-State Resistance
V
GS
= 12V, I
D
= 5.0A pulsed
V
GS
= 12V, I
D
= 8.0A pulsed
T
j
= +125°C
V
GS
= 12V, I
D
= 5.0A pulsed
Diode Forward Voltage
V
GS
= 0V, I
D
= 8.0A pulsed
Symbol
V
(BR)DSS
V
GS(th)1
V
GS(th)2
V
GS(th)3
I
GSS1
I
GSS2
I
DSS1
I
DSS2
I
DSS3
r
DS(on)1
r
DS(on)2
r
DS(on)3
V
SD
Min.
100
2.0
1.0
4.0
5.0
±100
±200
25
1.0
0.25
0.180
0.185
0.35
1.5
Max.
Unit
Vdc
Symbol
V
DS
V
GS
I
D1
I
D2
P
tl
R
ds(on)
T
op
, T
stg
Value
100
± 20
8.0
5.0
25
(1)
0.180
(2)
-55 to +150
Unit
Vdc
Vdc
Adc
Adc
W
Ω
°C
TO-205AF
(modified TO-39)
JANSR2N7261, JANSF2N7261
See Figure 1
Vdc
nAdc
µAdc
mAdc
mAdc
Ω
Ω
Ω
Vdc
18 PIN LEADLESS CHIP CARRIER
JANSR2N7261U, JANSF2N7261U
See Figure 2
T4-LDS-0119 Rev. 2 (101017)
Page 1 of 5

JANSR2N7261 Related Products

JANSR2N7261 JANSF2N7261U 2N7261U 2N7261 JANSR2N7261U
Description Power Field-Effect Transistor, 8A I(D), 100V, 0.35ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-205AF, MODIFIED TO-39, 3 PIN Power Field-Effect Transistor, 8A I(D), 100V, 0.35ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, LEADLESS PACKAGE-18 Power Field-Effect Transistor, 8A I(D), 100V, 0.35ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, LEADLESS PACKAGE-18 Power Field-Effect Transistor, 8A I(D), 100V, 0.35ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-205AF, MODIFIED TO-39, 3 PIN Power Field-Effect Transistor, 8A I(D), 100V, 0.35ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, LEADLESS PACKAGE-18
Objectid 1713985555 1817750355 1713985525 1713985528 1713985552
package instruction CYLINDRICAL, O-MBCY-W3 LEADLESS PACKAGE-18 CHIP CARRIER, R-XQCC-N15 CYLINDRICAL, O-MBCY-W3 LEADLESS PACKAGE-18
Contacts 2 18 18 2 18
Reach Compliance Code compliant compliant compliant unknown compliant
ECCN code EAR99 EAR99 EAR99 EAR99 EAR99
Shell connection DRAIN SOURCE SOURCE DRAIN SOURCE
Configuration SINGLE WITH BUILT-IN DIODE SINGLE WITH BUILT-IN DIODE SINGLE WITH BUILT-IN DIODE SINGLE WITH BUILT-IN DIODE SINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage 100 V 100 V 100 V 100 V 100 V
Maximum drain current (ID) 8 A 8 A 8 A 8 A 8 A
Maximum drain-source on-resistance 0.35 Ω 0.35 Ω 0.35 Ω 0.35 Ω 0.35 Ω
FET technology METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR
JESD-30 code O-MBCY-W3 R-XQCC-N15 R-XQCC-N15 O-MBCY-W3 R-XQCC-N15
Number of components 1 1 1 1 1
Number of terminals 3 15 15 3 15
Operating mode ENHANCEMENT MODE ENHANCEMENT MODE ENHANCEMENT MODE ENHANCEMENT MODE ENHANCEMENT MODE
Package body material METAL UNSPECIFIED UNSPECIFIED METAL UNSPECIFIED
Package shape ROUND RECTANGULAR RECTANGULAR ROUND RECTANGULAR
Package form CYLINDRICAL CHIP CARRIER CHIP CARRIER CYLINDRICAL CHIP CARRIER
Polarity/channel type N-CHANNEL N-CHANNEL N-CHANNEL N-CHANNEL N-CHANNEL
Certification status Qualified Qualified Not Qualified Not Qualified Qualified
surface mount NO YES YES NO YES
Terminal form WIRE NO LEAD NO LEAD WIRE NO LEAD
Terminal location BOTTOM QUAD QUAD BOTTOM QUAD
Transistor component materials SILICON SILICON SILICON SILICON SILICON
Is it Rohs certified? incompatible incompatible incompatible - incompatible
Guideline MIL-19500/601 MIL-19500/601 - - MIL-19500/601
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