IS61VF25636A-7.5B3 datasheet, PDF

Datasheet> All Categories > storage> storage> IS61VF25636A-7.5B3

IS61VF25636A-7.5B3: DescriptionCache SRAM, 256KX36, 7.5ns, CMOS, PBGA165, 13 X 15 MM, PLASTIC, BGA-165; Categorystorage storage; File Size630KB，32 Pages; ManufacturerIntegrated Silicon Solution ( ISSI )

Download Datasheet Parametric View All

IS61VF25636A-7.5B3 Overview

Cache SRAM, 256KX36, 7.5ns, CMOS, PBGA165, 13 X 15 MM, PLASTIC, BGA-165

IS61VF25636A-7.5B3 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Integrated Silicon Solution ( ISSI )
Objectid	2060286252
Parts packaging code	BGA
package instruction	TBGA, BGA165,11X15,40
Contacts	165
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
compound_id	6572563
Maximum access time	7.5 ns
Other features	FLOW-THROUGH ARCHITECTURE
Maximum clock frequency (fCLK)	117 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B165
JESD-609 code	e0
length	15 mm
memory density	9437184 bit
Memory IC Type	CACHE SRAM
memory width	36
Number of functions	1
Number of terminals	165
word count	262144 words
character code	256000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	256KX36
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TBGA
Encapsulate equivalent code	BGA165,11X15,40
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	2.5 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum standby current	0.045 A
Minimum standby current	2.38 V
Maximum slew rate	0.175 mA
Maximum supply voltage (Vsup)	2.625 V
Minimum supply voltage (Vsup)	2.375 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	13 mm

Preview

Download Datasheet

View All

IS61LF25636A IS61VF25636A IS64LF25636A

IS61LF51218A IS61VF51218A

256K x 36, 512K x 18

9 Mb SYNCHRONOUS FLOW-THROUGH

AUGUST 2009

STATIC RAM

FEATURES

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and

control

• Burst sequence control using MODE input

• Three chip enable option for simple depth expan-

sion and address pipelining

• Common data inputs and data outputs

• Auto Power-down during deselect

• Single cycle deselect

• Snooze MODE for reduced-power standby

• JTAG Boundary Scan for PBGA package

• Power Supply

LF: V

3.3V + 5%,

ddq

3.3V/2.5V + 5%

VF: V

2.5V + 5%,

ddq

2.5V + 5%

• JEDEC 100-Pin TQFP, 119-pin PBGA, and 165-

pin PBGA packages

• Lead-free available

• Automotive temperature available

DESCRIPTION

The

ISSI

IS61LF/VF25636A, IS64LF25636A and IS61LF/

VF51218A are high-speed, low-power synchronous

static RAMs designed to provide burstable, high-performance

memory for communication and networking applications.

The IS61LF/VF25636A and IS64LF25636A are organized

as 262,144 words by 36 bits. The IS61LF/VF51218A is

organized as 524,288 words by 18 bits. Fabricated with

ISSI

's advanced CMOS technology, the device integrates

a 2-bit burst counter, high-speed SRAM core, and high-

drive capability outputs into a single monolithic circuit. All

synchronous inputs pass through registers controlled by

a positive-edge-triggered single clock input.

Write cycles are internally self-timed and are initiated by the

rising edge of the clock input. Write cycles can be one to

four bytes wide as controlled by the write control inputs.

Separate byte enables allow individual bytes to be written.

Byte write operation is performed by using byte write en-

able (BWE) input combined with one or more individual

byte write signals (BWx). In addition, Global Write (GW)

is available for writing all bytes at one time, regardless of

the byte write controls.

Bursts can be initiated with either ADSP (Address Status

Processor) or ADSC (Address Status Cache Controller)

input pins. Subsequent burst addresses can be gener-

ated internally and controlled by the

ADV

(burst address

advance) input pin.

The mode pin is used to select the burst sequence order,

Linear burst is achieved when this pin is tied LOW. Inter-

leave burst is achieved when this pin is tied HIGH or left

floating.

FAST ACCESS TIME

Symbol

Parameter

Clock Access Time

Cycle Time

Frequency

-6.5

6.5

7.5

133

-7.5

7.5

8.5

117

Units

MHz

notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-

est version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc.

Rev. F

07/22/09

Recommended Resources

Bathroom wet hand drying remote control circuit

300A-18V three-phase thyristor voltage regulating electrolytic power supply circuit

Connection of music alarm detection components

Stabilized power supply circuit diagram that is not affected by input voltage changes

Toy harpsichord circuit

Leakage alarm voltage regulator

The industry's first 90nm automotive microcontroller chips: Freescale and STMicroelectronics, two leading semiconductor suppliers to the automotive industry, have introduced the first four automotive Power Architecture? microcontroller (MCU) products, which ar...; 1ying Automotive Electronics

The Wisdom of Asking Questions (Full Version + PDF Format): Download the Wisdom of Asking Questions (full version + PDF format)....; ermingpi Embedded System

WIO LINK Review—by ddllxxrr: WIO LINK Review 1: Post photos and light up the lights WIO LINK Review 2: WIO LINK features and hardware analysis WIO LINK Review 3: Hello eeworld... WIO LINK Review 3: Hello eeworld... WIO LINK Evalu...; okhxyyo RF/Wirelessly

Urgent! ! 111 Single Chip Microcomputer Application System Design: [align=left]Design a signal generator with MCS-51 series single-chip microcomputer as the core[/align][align=left]Display waveform frequencyDisplay waveform category (sine wave 01, square wave 02)[/al...; 人不范二枉少年 51mcu

New step-up DC/DC controller from Linear Technology for 42V automotive systems: Linear Technology Corporation has introduced the LTC3872, a current-mode step-up DC/DC controller with 550kHz operating frequency. The LTC3872 does not require a sense resistor, thus saving board spac...; frozenviolet Automotive Electronics

A question about 8255A, please help: Dear masters, I have a problem with 8255A that needs to be solved urgently. The details are as follows: After my 8255A is connected to the microcontroller, all three ports are in output mode. After po...; lijb920 Embedded System

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components