L7C109DM12 datasheet, PDF - EEWORLD Datasheet

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L7C109DM12: DescriptionStandard SRAM, 128KX8, 12ns, CMOS, CDIP32, 0.400 INCH, HERMETIC SEALED, SIDE BRAZED, DIP-32; Categorystorage storage; File Size167KB，9 Pages; ManufacturerLOGIC Devices; Websitehttp://www.logicdevices.com/

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L7C109DM12 Overview

Standard SRAM, 128KX8, 12ns, CMOS, CDIP32, 0.400 INCH, HERMETIC SEALED, SIDE BRAZED, DIP-32

L7C109DM12 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	LOGIC Devices
Objectid	1437332078
Parts packaging code	DIP
package instruction	DIP,
Contacts	32
Reach Compliance Code	unknown
ECCN code	3A001.A.2.C
compound_id	9606802
Maximum access time	12 ns
Other features	AUTOMATIC POWER DOWN; BATTERY BACKUP
JESD-30 code	R-CDIP-T32
length	40.64 mm
memory density	1048576 bit
Memory IC Type	STANDARD SRAM
memory width	8
Humidity sensitivity level	3
Number of functions	1
Number of terminals	32
word count	131072 words
character code	128000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	128KX8
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Maximum seat height	4.953 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
width	10.16 mm

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L7C108/109

DEVICES INCORPORATED

128K x 8 Static RAM (Low Power)

L7C108/109

DEVICES INCORPORATED

128K x 8 Static RAM (Low Power)

DESCRIPTION

The

L7C108

and

L7C109

are high-

performance, low-power CMOS static

RAMs. The storage circuitry is organ-

ized as 131,072 words by 8 bits per

word. The 8 Data In and Data Out

signals share I/O pins. The L7C108 has

a single active-low Chip Enable. The

L7C109 has two Chip Enables (one

active-low). These devices are available

in three speeds with maximum access

times from 10 ns to 15 ns.

Inputs and outputs are TTL compat-

ible. Operation is from a single +5 V

power supply. Power consumption

is 930 mW (typical) at 10 ns. Dissipa-

tion drops to 50 mW (typical) when

the memory is deselected.

consume only 1.5 mW (typical), at 3 V,

allowing effective battery backup

operation.

The L7C108 and L7C109 provide

asynchronous (unclocked) operation

with matching access and cycle times.

The Chip Enables and a three-state I/O

bus with a separate Output Enable

control simplify the connection of

several chips for increased storage

capacity.

Memory locations are specified on

address pins A

through A

. For the

L7C108, reading from a designated

location is accomplished by presenting

an address and driving CE

and OE

LOW while WE remains HIGH. For

the L7C109, CE

and OE must be

LOW while CE

and WE are HIGH.

The data in the addressed memory

location will then appear on the Data

Out pins within one access time. The

output pins stay in a high-impedance

state when CE

or OE is HIGH, or CE

(L7C109) or WE is LOW.

Writing to an addressed location is

accomplished when the active-low

and WE inputs are both LOW,

and CE

(L7C109) is HIGH. Any of

these signals may be used to terminate

the write operation. Data In and Data

Out signals have the same polarity.

Latchup and static discharge protection

are provided on-chip. The L7C108 and

L7C109 can withstand an injection

current of up to 200 mA on any pin

without damage.

FEATURES

128K x 8 Static RAM with Chip

Select Powerdown, Output Enable

Auto-Powerdown™ Design

Advanced CMOS Technology

High Speed — to 10 ns maximum

Low Power Operation

Active: 570 mW typical at 15 ns

Standby: 5 mW typical

Data Retention at 2 V for Battery

Backup Operation

DSCC SMD No. 5962-89598

Available 100% Screened to

MIL-STD-883, Class B

Plug Compatible with Cypress

CY7C108/109, IDT71024/71B024,

Micron MT5C1008, Motorola

MCM6226A/62L26A, Sony

CXK581020

Package Styles Available:

• 32-pin Sidebraze, Hermetic DIP

• 32-pin Plastic SOJ

• 32-pin Ceramic LCC

• 32-pin Ceramic SOJ

L7C108/109 B

LOCK

IAGRAM

ROW

ADDRESS

(L7C109 only)

ROW SELECT

CONTROL

512 x 256 x 8

MEMORY

ARRAY

COLUMN SELECT

& COLUMN SENSE

COLUMN ADDRESS

Two standby modes are available.

Proprietary Auto-Powerdown™

circuitry reduces power consumption

automatically during read or write

accesses which are longer than the

minimum access time, or when the

memory is deselected. In addition,

data may be retained in inactive

storage with a supply voltage as low

as 2 V. The L7C108 and L7C109

I/O

7-0

1M Static RAMs

03/04/99–LDS.108/9-N

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