MK50H25N33 datasheet, PDF - EEWORLD Datasheet

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MK50H25N33: Description1 CHANNEL(S), 51Mbps, SERIAL COMM CONTROLLER, PDIP48, PLASTIC, DIP-48; CategoryThe embedded processor and controller Microcontrollers and processors; File Size516KB，62 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/; Environmental Compliance

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MK50H25N33 Overview

1 CHANNEL(S), 51Mbps, SERIAL COMM CONTROLLER, PDIP48, PLASTIC, DIP-48

MK50H25N33 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	STMicroelectronics
Parts packaging code	DIP
package instruction	PLASTIC, DIP-48
Contacts	48
Reach Compliance Code	compliant
Address bus width	24
boundary scan	NO
Bus compatibility	68020; 68000; Z8000; 80386SX; 80286; 80186; 8086; 8088; Z80
maximum clock frequency	33 MHz
letter of agreement	SYNC HDLC; X.25; X.32; X.75; LAPB; LAPD
Maximum data transfer rate	6.375 MBps
External data bus width	16
JESD-30 code	R-PDIP-T48
JESD-609 code	e3
low power mode	NO
Number of serial I/Os	1
Number of terminals	48
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Matte Tin (Sn)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	15.24 mm
uPs/uCs/peripheral integrated circuit type	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL

MK50H25N33 Preview

MK50H25

HIGH SPEED

LINK LEVEL CONTROLLER

SECTION 1 - FEATURES

System clock rate up to 33 MHz (MK50H25 -

33), 25 MHz (MK50H25 - 25), or 16 MHz

(MK50H25 - 16).

Data rate up to 20 Mbps continuous

(MK50H25 - 33) or up to 51 Mbps bursted

On chip DMA control with programmable burst

length.

DMA transfer rate of up to 13.3 Mbytes/sec us-

ing optional 5 SYSCLK DMA cycle (150 nS) at

33 MHz SYSCLK.

Complete Level 2 implementation compatible

with X.25 LAPB, ISDN LAPD, X.32, and X.75

Protocols.

Handles all error recovery, sequencing, and S

and U frame control.

Pin-for-pin and architecturally compatible with

MK5025 (X.25/LAPD), MK5027 (CCS#7) and

MK5029(SDLC).

Buffer Management includes:

- Initialization Block

- Separate Receive and Transmit Rings

- Variable Descriptor Ring and Window Sizes.

Separate 64-byte Transmit and Receive FIFO.

Programmable Transmit FIFO hold-off water-

mark.

Handles all HDLC frame formatting:

- Zero bit insertion and deletion

- FCS (CRC) generation and detection

- Frame delimiting with flags

Programmable Single or Extended Address

and Control fields.

Five programmable timer/counters: T1, T3,

TP, N1, N2

Programmable minimum frame spacing on

transmission (number of flags between

frames).

- Programmable from 1 to 62 flags between

frames

Selectable FCS (CRC) of 16 or 32 bits, and

passing of entire FCS to buffer.

Testing Facilities:

- Internal Loopback

- Silent Loopback

- Optional Internal Data Clock Generation

- Self Test.

Programmable for full or half duplex operation

September 2003

DIP48

PLCC 52

Programmable Watchdog Timers for RCLK

and TCLK (to detect absence of data clocks)

Option causing received data to effectively be

odd-byte aligned, in addition to standard even-

byte alignment.

Available in 52 pin PLCC(for use with external

ROM), or 48 pin DIP packages.

SECTION 2 - INTRODUCTION

The STMicroelectronics MK50H25 Link Level

Controller is a VLSI semiconductor device which

provides complete link level data communications

control conforming to the 1984 and 1988 CCITT

versions of X.25. The MK50H25 will perform

frame formating including: frame delimiting with

flags, transparency (so-called "bit-stuffing"), error

recovery by retransmission, sequence number

control, S (supervisory) and U (unnumbered)

frame control, plus FCS (CRC) generation and

detection. The MK50H25 also supports X.75 and

X.32 (with its XID frame support), as well as sin-

gle channel ISDN LAPD (with its support of UI

frames and extended addressing capabilities).

1/62

MK50H25

DESCRIPTION

(Continued)

For added flexibility a transparent mode provides

an HDLC transport mechanism without link layer

support. This flexible transparent mode may be

easily entered and exited without affecting the

X.25 link status or the link state variables kept by

the MK50H25. In this mode no protocol process-

ing is done and it is up to the user to take care of

the upper level software. Single or extended Ad-

dress field filtering and Control field handling are

optionally supported within the transparent mode.

One of the outstanding features of the MK50H25

is its buffer management which includes on-chip

dual channel DMA. This feature allows users to

receive and transmit multiple data frames at a

time. (A conventional serial communications con-

trol chip plus a separate DMA chip would handle

data for only a single block at a time.) The

DIP48 PIN CONNECTION

(Top view)

MK50H25 will move multiple blocks of receive

and transmit data directly into and out of memory

through the Host’s bus. A possible system con-

figuration for the MK50H25 is shown in figure 1.

The MK50H25 may be used with any of several

popular 16 and 8 bit microprocessors, such as

68020, 68000, 6800, Z8000, Z80, 8086, 8088,

80186, 80286, 80386SX, etc.

The MK50H25 may be operated in either full or

half duplex mode. In half duplex mode, the RTS

and CTS modem control pins are provided. In full

duplex mode, these pins become user program-

mable I/O pins. All signal pins on the MK50H25

are TTL compatible. This has the advantage of

making the MK50H25 independent of the physical

interface. As shown in figure 1, line drivers and

receivers are used for electrical connection to the

physical layer.

VSS-GND

DAL07

DAL06

DAL05

DAL04

DAL03

DAL02

DAL01

DAL00

READ

INTR

DALI

DALO

DAS

BMO, BYTE, BUSREL

BMI, BUSAKO

HOLD, BUSRQ

ALE, AS

HLDA

ADR

READY

RESET

VSS-GND

VCC (+5V)

DAL08

DAL09

DAL10

DAL11

DAL12

DAL13

DAL14

DAL15

A16

A17

A18

A19

A20

A21

A22

A23

DSR, CTS

SYSCLK

RCLK

DTR, RTS

TCLK

2/62

MK50H25

PLCC52 PIN CONNECTION

(Top view)

DAL02

DAL01

DAL00

READ

INTR

DALI

DALO

DAS

BMO/BYTE/BUSREL

No Connect

BM1/BUSAKO

HOLD/BUSRQ

ALE/AS

8 7

No Connect

DAL03

DAL04

DAL05

DAL06

DAL07

VSS

VCC

DAL08

DAL09

DAL10

DAL11

DAL12

1 52

MK50H25Q

ADR

READY

RESET

VSS(GND)

No Connect

HLDA

TCLK

DTR/RTS

RCLK

SYSCLK

DSR/CTS

DAL13

DAL14

DAL15

A16

A17

A18

A19

A20

A21

A22

No Connect

A23

3/62

MK50H25

TAble 1:

PIN DESCRIPTION

LEGEND:

Input only

Input / Output

Open Drain (no internal pull-up)

Note:

Output only

3-State

Pin out for 52 pin PLCC is shown in brackets.

PIN(S)

2-9

40-47

[2-10

44-51]

[11]

TYPE

IO/3S

DESCRIPTION

The time multiplexed Data/Address bus. During the address portion of a

memory transfer, DAL<15:00> contains the lower 16 bits of the memory

address.

During the data portion of a memory transfer, DAL<15:00> contains the read

or write data, depending on the type of transfer.

READ indicates the type of operation that the bus controller is performing

during a bus transaction. READ is driven by the MK50H25 only while it is the

BUS MASTER. READ is valid during the entire bus transaction and is

tristated at all other times.

MK50H25 as a Bus Slave :

READ = HIGH - Data is placed on the DAL lines by the chip.

READ = LOW - Data is taken off the DAL lines by the chip.

MK50H25 as a Bus Master :

READ = HIGH - Data is taken off the DAL lines by the chip.

READ = LOW - Data is placed on the DAL lines by the chip.

INTERRUPT is an attention interrupt line that indicates that one or more of

the following CSR0 status flags is set: MISS, MERR, RINT, TINT or PINT.

INTERRUPT is enabled by CSR0<09>, INEA=1.

DAL IN is an external bus transceiver control line. DALI is driven by the

MK50H25 only while it is the BUS MASTER. DALI is asserted by the

MK50H25 when it reads from the DAL lines during the data portion of a

READ transfer. DALI is not asserted during a WRITE transfer.

DAL OUT is an external bus transceiver control line. DALO is driven by the

MK50H25 only while it is the BUS MASTER. DALO is asserted by the

MK50H25 when it drives the DAL lines during the address portion of a READ

transfer or for the duration of a WRITE transfer.

DATA STROBE defines the data portion of a bus transaction. By definition,

data is stable and valid at the low to high transition of DAS. This signal is

driven by the MK50H25 while it is the BUS MASTER. During the BUS

SLAVE operation, this pin is used as an input. At all other times the signal is

tristated.

I/O pins 15 and 16 are programmable through CSR4. If bit 06 of CSR4 is set

to a one, pin 15 becomes input BUSREL and is used by the host to signal

the MK50H25 to terminate a DMA burst after the current bus transfer has

completed. If bit 06 is clear then pin 15 is an output and behaves as

described below for pin 16.

Pins 15 and 16 are programmable through bit 00 of CSR4 (BCON).

If CSR4<00> BCON = 0,

I/O PIN 15 = BMO (O/3S)

I/O PIN 16 = BM1 (O/3S)

BYTE MASK<1:0> Indicates the byte(s) on the DAL to be read or written

during this bus transaction. MK50H25 drives these lines only as a Bus

Master. MK50H25 ignores the BM lines when it is a Bus Slave.

Byte selection is done as outlined in the following table.

BM1

BM0

TYPE OF TRANSFER

LOW

ENTIRE WORD

LOW

HIGH

UPPER BYTE

(DAL<15:08>)

HIGH

LOW

LOWER BYTE

(DAL<07:00>)

HIGH

NONE

SIGNAL NAME

DAL<15:00>

READ

IO/3S

INTR

[12]

[13]

O/OD

DALI

O/3S

DALO

[14]

O/3S

DAS

[15]

IO/3S

BMO

BYTE

BUSREL

[16]

IO/3S

BM1

BUSAKO

[18]

O/3S

4/62

MK50H25

Table 1:

PIN DESCRIPTION (continued)

SIGNAL NAME

PIN(S)

TYPE

DESCRIPTION

If CSR4<00> BCON = 1,

I/O PIN 15 = BYTE (O/3S)

I/O PIN 16 = BUSAKO (O)

Byte selection is done using the BYTE line and DAL<00> latched during the

address portion of the bus transaction. MK50H25 drives BYTE only as a Bus

Master and ignores it when a Bus Slave. Byte selection is done as outlined

in the following table.

BYTE

DAL<00>

TYPE OF TRANSFER

LOW

ENTIRE WORD

LOW

HIGH

ILLEGAL CONDITION

HIGH

LOW

LOWER BYTE

HIGH

UPPER BYTE

BUSAKO is a bus request daisy chain output. If MK50H25 is not requesting

the bus and it receives HLDA, BUSAKO will be driven low. If MK50H25 is

requesting the bus when it receives HLDA, BUSAKO will remain high

Note: All transfers are entire word unless the MK50H25 is configured for 8 bit

operation.

HOLD

BUSRQ

[19]

IO/OD

Pin 17 is configured through bit 0 of CSR4.

If CSR4<00> BCON = 0,

I/O PIN 17 = HOLD

HOLD request is asserted by MK50H25 when it requires a DMA cycle, if

HLDA is inactive, regardless of the previous state of the HOLD pin. HOLD is

held low for the entire ensuing bus transaction.

If CSR4<00> BCON = 1,

I/O PIN 17 = BUSRQ

BUSRQ is asserted by MK50H25 when it requires a DMA cycle if the prior

state of the BUSRQ pin was high and HLDA is inactive. BUSRQ is held low

for the entire ensuing bus transaction.

The active level of ADDRESS STROBE is programmable through CSR4.

The address portion of a bus transfer occurs while this signal is at its

asserted level. This signal is driven by MK50H25 while it is the BUS

MASTER. At all other times, the signal is tristated.

If CSR4<01> ACON = 0,

I/O PIN 18 = ALE

ADDRESS LATCH ENABLE is used to demultiplex the DAL lines and define

the address portion of the transfer. As ALE, the signal transitions from high

to low during the address portion of the transfer and remains low during the

data portion.

If CSR4<01> ACON = 1,

I/O PIN 18 = AS

As AS, the signal pulses low during the address portion of the bus transfer.

The low to high transition of AS can be used by a slave device to strobe the

address into a register.

AS is effectively the inversion of ALE.

HOLD ACKNOWLEDGE is the response to HOLD. When HLDA is low in

response to MK50H25’s assertion of HOLD, the MK50H25 is the Bus

Master. HLDA should be deasserted ONLY after HOLD has been released

by the MK50H25.

CHIP SELECT indicates, when low, that the MK50H25 is the slave device

for the data transfer. CS must be valid throughout the entire transaction.

ADDRESS selects the Register Address Port or the Register Data Port. It

must be valid throughout the data portion of the transfer and is only used by

the chip when CS is low.

ADR

PORT

LOW

HIGH

When the MK50H25 is a Bus Master, READY is an asynchronous

acknowledgement from the bus memory that memory will accept data in a

WRITE cycle or that memory has put data on the DAL lines in a READ cycle.

ALE

[20]

O/3S

HLDA

[21]

ADR

[22]

[23]

READY

[24]

IO/OD

5/62

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MK50H25N33 Related Products

	MK50H25N33	MK50H25Q25	MK50H25Q16	MK50H25-84Q33	MK50H25N25	MK50H25Q33	MK50H25-84Q16	MK50H25-84Q25	MK50H25N16
Description	1 CHANNEL(S), 51Mbps, SERIAL COMM CONTROLLER, PDIP48, PLASTIC, DIP-48	1 CHANNEL(S), SERIAL COMM CONTROLLER, PQCC52, PLASTIC, LCC-52	1 CHANNEL(S), SERIAL COMM CONTROLLER, PQCC52, PLASTIC, LCC-52	1 CHANNEL(S), 51Mbps, SERIAL COMM CONTROLLER, PQCC84, PLASTIC, LCC-84	1 CHANNEL(S), SERIAL COMM CONTROLLER, PDIP48, PLASTIC, DIP-48	1 CHANNEL(S), 51Mbps, SERIAL COMM CONTROLLER, PQCC52, PLASTIC, LCC-52	1 CHANNEL(S), SERIAL COMM CONTROLLER, PQCC84, PLASTIC, LCC-84	1 CHANNEL(S), SERIAL COMM CONTROLLER, PQCC84, PLASTIC, LCC-84	1 CHANNEL(S), SERIAL COMM CONTROLLER, PDIP48, PLASTIC, DIP-48
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to	conform to	conform to	conform to	conform to
Maker	STMicroelectronics	STMicroelectronics	STMicroelectronics	STMicroelectronics	STMicroelectronics	STMicroelectronics	STMicroelectronics	STMicroelectronics	STMicroelectronics
Parts packaging code	DIP	LCC	LCC	LCC	DIP	LCC	LCC	LCC	DIP
package instruction	PLASTIC, DIP-48	QCCJ,	PLASTIC, LCC-52	PLASTIC, LCC-84	PLASTIC, DIP-48	PLASTIC, LCC-52	PLASTIC, LCC-84	PLASTIC, LCC-84	PLASTIC, DIP-48
Contacts	48	52	52	84	48	52	84	84	48
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant	compliant	compli	compli
Address bus width	24	24	24	24	24	24	24	24	24
boundary scan	NO	NO	NO	NO	NO	NO	NO	NO	NO
Bus compatibility	68020; 68000; Z8000; 80386SX; 80286; 80186; 8086; 8088; Z80	68020; 68000; Z8000; 80386SX; 80286; 80186; 8086; 8088; Z80	68020; 68000; Z8000; 80386SX; 80286; 80186; 8086; 8088; Z80	68020; 68000; Z8000; 80386SX; 80286; 80186; 8086; 8088; Z80	68020; 68000; Z8000; 80386SX; 80286; 80186; 8086; 8088; Z80	68020; 68000; Z8000; 80386SX; 80286; 80186; 8086; 8088; Z80	68020; 68000; Z8000; 80386SX; 80286; 80186; 8086; 8088; Z80	68020; 68000; Z8000; 80386SX; 80286; 80186; 8086; 8088; Z80	68020; 68000; Z8000; 80386SX; 80286; 80186; 8086; 8088; Z80
maximum clock frequency	33 MHz	25 MHz	16 MHz	33 MHz	25 MHz	33 MHz	16 MHz	25 MHz	16 MHz
letter of agreement	SYNC HDLC; X.25; X.32; X.75; LAPB; LAPD	SYNC HDLC; X.25; X.32; X.75; LAPB; LAPD	SYNC HDLC; X.25; X.32; X.75; LAPB; LAPD	SYNC HDLC; X.25; X.32; X.75; LAPB; LAPD	SYNC HDLC; X.25; X.32; X.75; LAPB; LAPD	SYNC HDLC; X.25; X.32; X.75; LAPB; LAPD	SYNC HDLC; X.25; X.32; X.75; LAPB; LAPD	SYNC HDLC; X.25; X.32; X.75; LAPB; LAPD	SYNC HDLC; X.25; X.32; X.75; LAPB; LAPD
External data bus width	16	16	16	16	16	16	16	16	16
JESD-30 code	R-PDIP-T48	S-PQCC-J52	S-PQCC-J52	S-PQCC-J84	R-PDIP-T48	S-PQCC-J52	S-PQCC-J84	S-PQCC-J84	R-PDIP-T48
JESD-609 code	e3	e3	e3	e3	e3	e3	e3	e3	e3
low power mode	NO	NO	NO	NO	NO	NO	NO	NO	NO
Number of serial I/Os	1	1	1	1	1	1	1	1	1
Number of terminals	48	52	52	84	48	52	84	84	48
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	DIP	QCCJ	QCCJ	QCCJ	DIP	QCCJ	QCCJ	QCCJ	DIP
Package shape	RECTANGULAR	SQUARE	SQUARE	SQUARE	RECTANGULAR	SQUARE	SQUARE	SQUARE	RECTANGULAR
Package form	IN-LINE	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER	IN-LINE	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum supply voltage	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V
Minimum supply voltage	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V
Nominal supply voltage	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	NO	YES	YES	YES	NO	YES	YES	YES	NO
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Matte Tin (Sn)	Matte Tin (Sn)	Matte Tin (Sn)	Matte Tin (Sn)	Matte Tin (Sn)	Matte Tin (Sn)	Matte Tin (Sn)	Matte Tin (Sn)	Matte Tin (Sn)
Terminal form	THROUGH-HOLE	J BEND	J BEND	J BEND	THROUGH-HOLE	J BEND	J BEND	J BEND	THROUGH-HOLE
Terminal pitch	2.54 mm	1.27 mm	1.27 mm	1.27 mm	2.54 mm	1.27 mm	1.27 mm	1.27 mm	2.54 mm
Terminal location	DUAL	QUAD	QUAD	QUAD	DUAL	QUAD	QUAD	QUAD	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	15.24 mm	19.05 mm	19.05 mm	29.21 mm	15.24 mm	19.05 mm	29.21 mm	29.21 mm	15.24 mm
uPs/uCs/peripheral integrated circuit type	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL
length	-	19.05 mm	19.05 mm	29.21 mm	-	19.05 mm	29.21 mm	29.21 mm	-
Maximum seat height	-	5.08 mm	5.08 mm	5.08 mm	-	5.08 mm	5.08 mm	5.08 mm	-

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