IDTCV142PA datasheet, PDF - EEWORLD Datasheet

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IDTCV142PA: DescriptionProcessor Specific Clock Generator, 400MHz, PDSO56, TSSOP-56; CategoryThe embedded processor and controller Microcontrollers and processors; File Size112KB，20 Pages; ManufacturerIDT (Integrated Device Technology)

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IDTCV142PA Overview

Processor Specific Clock Generator, 400MHz, PDSO56, TSSOP-56

IDTCV142PA Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	TSSOP
package instruction	TSSOP, SSOP56,.4
Contacts	56
Reach Compliance Code	not_compliant
ECCN code	EAR99
JESD-30 code	R-PDSO-G56
JESD-609 code	e0
length	14 mm
Humidity sensitivity level	1
Number of terminals	56
Maximum operating temperature	70 °C
Minimum operating temperature
Maximum output clock frequency	400 MHz
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	SSOP56,.4
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	240
power supply	3.3 V
Master clock/crystal nominal frequency	14.31818 MHz
Certification status	Not Qualified
Maximum seat height	1.1 mm
Maximum slew rate	400 mA
Maximum supply voltage	3.465 V
Minimum supply voltage	3.135 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	20
width	6.1 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, PROCESSOR SPECIFIC

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IDTCV142

PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR

COMMERCIAL TEMPERATURE RANGE

PROGRAMMABLE FLEXPC

CLOCK FOR P4 PROCESSOR

IDTCV142

FEATURES:

• Power management control suitable for notebook applications

• One high precision PLL for CPU, SSC and N programming

• One high precision PLL for SRC/PCI, supports 100MHz output

frequency, SSC and N programming

• One high precision PLL for 96MHz/48MHz

• Band-gap circuit for differential outputs

• Support spread spectrum modulation, –0.5 down spread and

others

• Support SMBus block read/write, index read/write

• Selectable output strength for REF

• Allows for CPU frequency to change to a slower frequency to

conserve power when an application is less execution-

intensive

• Smooth transition for N programming

• Available in TSSOP package

DESCRIPTION:

IDTCV142 is a 56 pin clock device, complying with Intel CK410M requirements

for Intel advance P4 processors. The CPU output buffer is designed to support

up to 400MHz processor. This chip has three PLLs inside for CPU, SRC/PCI,

and 48MHz/DOT96 IO clocks. This device also implements Band-gap

referenced I

REF

to reduce the impact of V

variation on differential outputs,

which can provide more robust system performance. Each CPU/SRC has its

own Spread Spectrum selection.

OUTPUTS:

•

2*0.7V current –mode differential CPU CLK pair

6*0.7V current –mode differential SRC CLK pair

One CPU_ITP/SRC selectable CLK pair

6*PCI, 2 free running, 33.3MHz

1*96MHz, 1*48MHz

1*REF

KEY SPECIFICATIONS:

• CPU/SRC CLK cycle to cycle jitter < 85ps

• SATA CLK cycle to cycle jitter < 85ps

• PCI CLK cycle to cycle jitter < 250ps

FUNCTIONAL BLOCK DIAGRAM

PLL1

SSC

N Programmable

CPU CLK

Output Buffer

Stop Logic

CPU[1:0]

XTAL_IN

XTAL

Osc Amp

CPU_ITP/SRC7

REF

ITP_EN

XTAL_OUT

SDATA

SCLK

SM Bus

Controller

PLL2

SSC

N Programmable

SRC CLK

Output Buffer

Stop Logic

SRC[5:1]

PCI[3:0], PCIF[1:0]

TT_

WRGD

#/PD

SEL100/96#

CLKREQA#

CLKREQB#

FSA.B.C

PCI_STOP#

CPU_STOP#

Control

Logic

PLL3

48MHz/96MHz

Output BUffer

DOT96

SEL

100/96MHz

48MHz

REF

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE

FEBRUARY 2005

DSC 6584/18

IDTCV142PA Related Products

	IDTCV142PA	CV142PAG8	CV142PAG
Description	Processor Specific Clock Generator, 400MHz, PDSO56, TSSOP-56	Processor Specific Clock Generator, 400MHz, PDSO56, GREEN, TSSOP-56	Processor Specific Clock Generator, 400MHz, PDSO56, GREEN, TSSOP-56
Is it Rohs certified?	incompatible	conform to	conform to
Parts packaging code	TSSOP	TSSOP	TSSOP
package instruction	TSSOP, SSOP56,.4	GREEN, TSSOP-56	TSSOP, SSOP56,.4
Contacts	56	56	56
Reach Compliance Code	not_compliant	unknown	unknown
ECCN code	EAR99	EAR99	EAR99
JESD-30 code	R-PDSO-G56	R-PDSO-G56	R-PDSO-G56
JESD-609 code	e0	e3	e3
length	14 mm	14 mm	14 mm
Humidity sensitivity level	1	1	1
Number of terminals	56	56	56
Maximum operating temperature	70 °C	70 °C	70 °C
Maximum output clock frequency	400 MHz	400 MHz	400 MHz
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	TSSOP	TSSOP
Encapsulate equivalent code	SSOP56,.4	SSOP56,.4	SSOP56,.4
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	240	260	260
power supply	3.3 V	3.3 V	3.3 V
Master clock/crystal nominal frequency	14.31818 MHz	14.31818 MHz	14.31818 MHz
Certification status	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.1 mm	1.1 mm	1.1 mm
Maximum slew rate	400 mA	400 mA	400 mA
Maximum supply voltage	3.465 V	3.465 V	3.465 V
Minimum supply voltage	3.135 V	3.135 V	3.135 V
Nominal supply voltage	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed
Terminal form	GULL WING	GULL WING	GULL WING
Terminal pitch	0.5 mm	0.5 mm	0.5 mm
Terminal location	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	20	30	30
width	6.1 mm	6.1 mm	6.1 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, PROCESSOR SPECIFIC	CLOCK GENERATOR, PROCESSOR SPECIFIC	CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches	-	1	1

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