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CV142PAG8

Description
Processor Specific Clock Generator, 400MHz, PDSO56, GREEN, TSSOP-56
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size112KB,20 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
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CV142PAG8 Overview

Processor Specific Clock Generator, 400MHz, PDSO56, GREEN, TSSOP-56

CV142PAG8 Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
Parts packaging codeTSSOP
package instructionGREEN, TSSOP-56
Contacts56
Reach Compliance Codeunknown
ECCN codeEAR99
JESD-30 codeR-PDSO-G56
JESD-609 codee3
length14 mm
Humidity sensitivity level1
Number of terminals56
Maximum operating temperature70 °C
Minimum operating temperature
Maximum output clock frequency400 MHz
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeSSOP56,.4
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Master clock/crystal nominal frequency14.31818 MHz
Certification statusNot Qualified
Maximum seat height1.1 mm
Maximum slew rate400 mA
Maximum supply voltage3.465 V
Minimum supply voltage3.135 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width6.1 mm
uPs/uCs/peripheral integrated circuit typeCLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches1
IDTCV142
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PROGRAMMABLE FLEXPC
CLOCK FOR P4 PROCESSOR
IDTCV142
FEATURES:
• Power management control suitable for notebook applications
• One high precision PLL for CPU, SSC and N programming
• One high precision PLL for SRC/PCI, supports 100MHz output
frequency, SSC and N programming
• One high precision PLL for 96MHz/48MHz
• Band-gap circuit for differential outputs
• Support spread spectrum modulation, –0.5 down spread and
others
• Support SMBus block read/write, index read/write
• Selectable output strength for REF
• Allows for CPU frequency to change to a slower frequency to
conserve power when an application is less execution-
intensive
• Smooth transition for N programming
• Available in TSSOP package
DESCRIPTION:
IDTCV142 is a 56 pin clock device, complying with Intel CK410M requirements
for Intel advance P4 processors. The CPU output buffer is designed to support
up to 400MHz processor. This chip has three PLLs inside for CPU, SRC/PCI,
and 48MHz/DOT96 IO clocks. This device also implements Band-gap
referenced I
REF
to reduce the impact of V
DD
variation on differential outputs,
which can provide more robust system performance. Each CPU/SRC has its
own Spread Spectrum selection.
OUTPUTS:
2*0.7V current –mode differential CPU CLK pair
6*0.7V current –mode differential SRC CLK pair
One CPU_ITP/SRC selectable CLK pair
6*PCI, 2 free running, 33.3MHz
1*96MHz, 1*48MHz
1*REF
KEY SPECIFICATIONS:
• CPU/SRC CLK cycle to cycle jitter < 85ps
• SATA CLK cycle to cycle jitter < 85ps
• PCI CLK cycle to cycle jitter < 250ps
FUNCTIONAL BLOCK DIAGRAM
PLL1
SSC
N Programmable
CPU CLK
Output Buffer
Stop Logic
CPU[1:0]
XTAL_IN
XTAL
Osc Amp
CPU_ITP/SRC7
I
REF
REF
ITP_EN
XTAL_OUT
SDATA
SCLK
SM Bus
Controller
PLL2
SSC
N Programmable
SRC CLK
Output Buffer
Stop Logic
SRC[5:1]
PCI[3:0], PCIF[1:0]
V
TT_
P
WRGD
#/PD
SEL100/96#
CLKREQA#
CLKREQB#
FSA.B.C
PCI_STOP#
CPU_STOP#
Control
Logic
PLL3
48MHz/96MHz
Output BUffer
DOT96
SEL
100/96MHz
48MHz
I
REF
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
© 2005 Integrated Device Technology, Inc.
FEBRUARY 2005
DSC 6584/18

CV142PAG8 Related Products

CV142PAG8 CV142PAG IDTCV142PA
Description Processor Specific Clock Generator, 400MHz, PDSO56, GREEN, TSSOP-56 Processor Specific Clock Generator, 400MHz, PDSO56, GREEN, TSSOP-56 Processor Specific Clock Generator, 400MHz, PDSO56, TSSOP-56
Is it Rohs certified? conform to conform to incompatible
Parts packaging code TSSOP TSSOP TSSOP
package instruction GREEN, TSSOP-56 TSSOP, SSOP56,.4 TSSOP, SSOP56,.4
Contacts 56 56 56
Reach Compliance Code unknown unknown not_compliant
ECCN code EAR99 EAR99 EAR99
JESD-30 code R-PDSO-G56 R-PDSO-G56 R-PDSO-G56
JESD-609 code e3 e3 e0
length 14 mm 14 mm 14 mm
Humidity sensitivity level 1 1 1
Number of terminals 56 56 56
Maximum operating temperature 70 °C 70 °C 70 °C
Maximum output clock frequency 400 MHz 400 MHz 400 MHz
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSSOP TSSOP TSSOP
Encapsulate equivalent code SSOP56,.4 SSOP56,.4 SSOP56,.4
Package shape RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius) 260 260 240
power supply 3.3 V 3.3 V 3.3 V
Master clock/crystal nominal frequency 14.31818 MHz 14.31818 MHz 14.31818 MHz
Certification status Not Qualified Not Qualified Not Qualified
Maximum seat height 1.1 mm 1.1 mm 1.1 mm
Maximum slew rate 400 mA 400 mA 400 mA
Maximum supply voltage 3.465 V 3.465 V 3.465 V
Minimum supply voltage 3.135 V 3.135 V 3.135 V
Nominal supply voltage 3.3 V 3.3 V 3.3 V
surface mount YES YES YES
technology CMOS CMOS CMOS
Temperature level COMMERCIAL COMMERCIAL COMMERCIAL
Terminal surface Matte Tin (Sn) - annealed Matte Tin (Sn) - annealed Tin/Lead (Sn85Pb15)
Terminal form GULL WING GULL WING GULL WING
Terminal pitch 0.5 mm 0.5 mm 0.5 mm
Terminal location DUAL DUAL DUAL
Maximum time at peak reflow temperature 30 30 20
width 6.1 mm 6.1 mm 6.1 mm
uPs/uCs/peripheral integrated circuit type CLOCK GENERATOR, PROCESSOR SPECIFIC CLOCK GENERATOR, PROCESSOR SPECIFIC CLOCK GENERATOR, PROCESSOR SPECIFIC
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