IBM25PPC750CXEJP2013T datasheet, PDF

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IBM25PPC750CXEJP2013T: DescriptionRISC Microprocessor, 32-Bit, 400MHz, CMOS, PBGA256, 27 X 27 MM, PLASTIC, BGA-256; CategoryThe embedded processor and controller Microcontrollers and processors; File Size417KB，44 Pages; ManufacturerIBM; Websitehttp://www.ibm.com

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IBM25PPC750CXEJP2013T Overview

RISC Microprocessor, 32-Bit, 400MHz, CMOS, PBGA256, 27 X 27 MM, PLASTIC, BGA-256

IBM25PPC750CXEJP2013T Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	IBM
Objectid	1935829549
Parts packaging code	BGA
package instruction	LBGA, BGA256,20X20,50
Contacts	256
Reach Compliance Code	not_compliant
ECCN code	3A001.A.3
compound_id	451174
Address bus width	32
bit size	32
boundary scan	YES
maximum clock frequency	133 MHz
External data bus width	64
Format	FLOATING POINT
Integrated cache	YES
JESD-30 code	S-PBGA-B256
length	27 mm
low power mode	YES
Number of terminals	256
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Encapsulate equivalent code	BGA256,20X20,50
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE
power supply	1.8,1.8/2.5 V
Certification status	Not Qualified
Maximum seat height	1.666 mm
speed	400 MHz
Maximum supply voltage	1.9 V
Minimum supply voltage	1.7 V
Nominal supply voltage	1.8 V
surface mount	YES
technology	CMOS
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
width	27 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC

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PowerPC

750CXe RISC Microprocessor

Data Sheet

Version: 1.5

(For DD3.1 Only)

Preliminary

April 8, 2004

Preliminary

Data Sheet

PowerPC 750CXe RISC Microprocessor

Table of Contents

List of Tables ................................................................................................................. iii

List of Figures ................................................................................................................ v

1. General Information .................................................................................................... 1

1.1 Features ...........................................................................................................................................

1.2 Special Design Level Considerations/Features ...........................................................................

1.3 Ordering Information ......................................................................................................................

1.4 Processor Version Register (PVR) ................................................................................................

2. Overview ...................................................................................................................... 5

2.1 PowerPC 750CXe Block Diagram .................................................................................................. 5

3. General Parameters .................................................................................................... 6

4. Electrical and Thermal Characteristics ..................................................................... 7

4.1 DC Electrical Characteristics ......................................................................................................... 7

4.2 AC Electrical Characteristics ....................................................................................................... 10

4.2.1 Clock AC Specifications ........................................................................................................ 10

4.3 Spread Spectrum Clock Generator (SSCG) ................................................................................ 11

4.4 60x Bus Input AC Specifications ................................................................................................. 12

4.5 60x Bus Output AC Specifications .............................................................................................. 13

4.5.1 IEEE 1149.1 AC Timing Specifications ................................................................................. 16

5. PowerPC 750CXe Dimension and Physical Signal Assignments ........................ 18

6. System Design Information ..................................................................................... 26

6.1 PLL Configuration .........................................................................................................................

6.2 PLL Power Supply Filtering .........................................................................................................

6.3 Decoupling Recommendations ...................................................................................................

6.4 Connection Recommendations ...................................................................................................

6.5 Output Buffer DC Impedance .......................................................................................................

6.5.1 Input-Output Usage ...............................................................................................................

6.6 Thermal Management Information ..............................................................................................

6.6.1 Thermal Assist Unit ...............................................................................................................

6.6.2 Heat Sink Considerations ......................................................................................................

6.6.3 Internal Package Conduction Resistance ..............................................................................

6.7 Operational and Design Considerations .....................................................................................

6.7.1 Level Protection .....................................................................................................................

6.7.2 64- or 32-Bit Data Bus Mode .................................................................................................

6.7.3 60x Bus Operation .................................................................................................................

6.7.4 DBWO/L2_TSTCLK ...............................................................................................................

6.7.5 CHKSTP_OUT/CLKOUT .......................................................................................................

750cxe_TOC.fm.1.5

April 8, 2004

Page i of 36

Preliminary

Data Sheet

PowerPC 750CXe RISC Microprocessor

List of Tables

Table 1-1. Process Version Register (PVR) ................................................................................................... 4

Table 3-1. General Parameters ...................................................................................................................... 6

Table 4-1. Absolute Maximum Ratings ........................................................................................................... 7

Table 4-2. Recommended Operating Conditions ........................................................................................... 7

Table 4-3. Package Thermal Characteristics ................................................................................................. 8

Table 4-4. DC Electrical Specifications .......................................................................................................... 8

Table 4-5. Power Consumption ...................................................................................................................... 9

Table 4-6. Clock AC Timing Specifications

1,6

....................................................................................................................... 10

.............................................................................................................. 12

................................................................................................ 13

Table 4-7. 60x Bus Input Timing Specifications

1,6

Table 4-8. 60x Bus Output AC Timing Specifications

1,4,6

Table 4-9. JTAG AC Timing Specifications (Independent of SYSCLK) ........................................................ 16

Table 5-1. Signal Listing for the 256 PBGA Package ................................................................................... 22

Table 5-2. PPC750 Signals Not Supported in the 750CXe .......................................................................... 23

Table 5-3. Signal Locations .......................................................................................................................... 24

Table 5-4. Voltage and Ground Assignments ............................................................................................... 25

Table 6-1. PowerPC 750CXe Microprocessor PLL Configuration ................................................................ 26

Table 6-2. Driver Impedance Characteristics ............................................................................................... 29

Table 6-3. Input-Output Usage ..................................................................................................................... 30

750cxe_LOT.fm.1.5

April 8, 2004

List of Tables

Page iii of 36

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