DATASHEET
Frequency Generator with 133MHz Differential
CPU Clocks
Recommended Application:
Servers based on Intel CK408 processors
Output Features:
•
4 Differential CPU Clock Pairs @ 3.3V
•
7 PCI (3.3V) @ 33.3MHz
•
3 PCI_F (3.3V) @ 33.3MHz
•
1 USB (3.3V) @ 48MHz
•
1 DOT (3.3V) @ 48MHz
•
1 REF (3.3V) @ 14.318MHz
•
1 3V66 (3.3V) @ 66.6MHz
•
1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz
•
3 66MHz_OUT/3V66 (3.3V) @ 66.6MHz_IN
or 66.6MHz
•
1 66MHz_IN/3V66 (3.3V) @ Input/66MHz
Features:
•
Supports spread spectrum modulation,
down spread 0 to -0.5%.
•
Efficient power management scheme through PD#
and PCI_STOP#.
•
Uses external 14.318MHz crystal
•
Stop clocks and functional control available through
SMBus interface.
Key Specifications:
•
CPU Output Jitter <150ps
•
3V66 Output Jitter <250ps
•
CPU Output Skew <150ps
Pin Configuration
ICS932S203
56-Pin 300mil SSOP/TSSOP
* These inputs have 150K internal pull-up resistor to VDD.
Block Diagram
Functionality
FS1 FS0
1
1
0
0
mid
mid
0
1
0
1
0
1
CPU
(MHz)
100
133.3
100
133.3
Hi-Z
Tclk/2
3V66
(MHz)
66.6
66.6
66.6
66.6
Hi-Z
Tclk/4
66Buff[2:0]
3V66[4:2]
(MHz)
66.6 In path
66. In path
66.6
66.6
Hi-Z
Tclk/4
PCI_F
PCI
(MHz)
66.6 in/2
66.6 in/2
33.3
33.3
Hi-Z
Tclk/8
IDT
TM
Frequency Generator with 133MHz Differential CPU Clocks
0601G—01/26/10
1
ICS932S203
Frequency Generator with 133MHz Differential CPU Clocks
Pin Description
PIN NUMBER
1, 8, 14, 19, 26,
32, 37, 46, 50
2
3
7, 6, 5
4, 9, 15, 20, 27,
31, 36, 41, 47
18, 17, 16, 13,
12,11, 10
23, 22, 21
24
25
PIN NAME
VDD
X1
X2
PCICLK_F (2:0)
GND
PCICLK (6:0)
66MHz_OUT (2:0)
3V66 (4:2)
66MHz_IN
3V66_5
PD#
TYPE
PWR
X2 Cr ystal Input
X1 Cr ystal
Output
OUT
PWR
OUT
OUT
OU T
IN
OU T
IN
3.3V power supply
14.318MHz Cr ystal input
14.318MHz Cr ystal output
DESCRIPTION
Free running PCI clock not affected by PCI_STOP# for power management.
Ground pins for 3.3V supply
PCI clock outputs
66MHz buffered 66MHz_OUT from 66MHz_IN input.
66MHz reference clocks, from internal VCO
66MHz input to buffered 66MHz_OUT and PCI clocks
66MHz reference clock, from internal VCO
Invokes power-down mode. Active Low.
28
Vtt_PWRGD#
IN
I/O
IN
OUT
IN
OUT
OUT
OUT
IN
OUT
IN
OUT
OUT
OUT
This 3.3V LVTTL input is a level sensitive strobe used to determine
when FS[0:2] and MULTISEL0 inputs are valid and are ready to be
sampled
(active low)
Data pin for SMBus circuitr y 5V tolerant
Clock pin of SMBus circuitr y 5V tolerant
66MHz reference clocks, from internal VCO
Halts PCICLK clocks at logic 0 level, when input low except
PCICLK_F which are free running
3.3V output selectable through
I
2
C
to be 66MHz from internal VCO or
48MHz (non-SSC)
48MHz output clock for DOT
48MHz output clock for USB
Special 3.3V input for Mode selection
This pin establishes the reference current for the CPUCLK pairs. This pin
requires a fixed precision resistor tied to ground in order to establish the
appropriate current.
MULTSEL0 input is sensed on power-up and then internally latched prior to
the pin being used for output on 3V 14.318MHz clocks.
"Complementar y" clocks of differential pair CPU outputs. These are current
outputs and external resistors are required for voltage bias.
"True" clocks of differential pair CPU outputs. These are current outputs and
external resistors are required for voltage bias.
14.318MHz reference clock.
29
30
33
34
35
38
39
40, 55
42
43
44, 48, 51, 53
45, 49, 52, 54
56
SDATA
SCLK
3V66_0
PCI_STOP#
3V66_1/VCH_CLK
48MHz_DOT
48MHz_USB
FS (1:0)
I REF
MULTSEL0
CPUCLKC (3:0)
CPUCLKT (3:0)
REF
Power Groups
(Analog)
VDDA = PLL1
VDD48 = 48MHz, PLL
VDDREF = VDD for Xtal, POR
(Digital)
VDDPCI
VDD3V66
VDDCPU
IDT
TM
Frequency Generator with 133MHz Differential CPU Clocks
0601G—01/26/10
2
ICS932S203
Frequency Generator with 133MHz Differential CPU Clocks
Frequency Select Table
FS1
1
1
0
0
mid
1
mid
1
FS0
0
1
0
1
0
1
CPU
100
133.3
100
133.3
Hi-Z
Tclk/2
3V66 (1:0)
66.6
66.6
66.6
66.6
Hi-Z
Tclk/4
66Buff (2:0) /
3V66 (4:2)
66.6 In path
66.6 In path
66.6
66.6
Hi-Z
Tclk/4
66 In /
3V66_5
66.6 IN
66.6 IN
66.6
66.6
Hi-Z
Tclk/4
PCI
66.6 in/2
66.6 in/2
33.3
33.3
Hi-Z
Tclk/8
REF
14.318
14.318
14.318
14.318
Hi-Z
Tclk
USB,
DOT
48
48
48
48
Hi-Z
Tclk/2
note
Buffer
mode 66
Buffer
mode 66
Driven 66
Driven 66
Tri-state
outputs
Tclk is at
X1 input
1. Low=Vin < 0.8V, Mid=1.0V < Vin < 1.8V, High=Vin > 2.0V
Host Swing Select Functions
Board Target
Trace/Term Z
50 ohms
50 ohms
Reference R,
Iref =
V
DD
/(3*Rr)
Rr = 221 1%,
Iref = 5.00mA
Rr = 475 1%,
Iref = 2.32mA
Output
Current
Ioh = 4* I REF
Ioh = 6* I REF
MULTISEL0
Voh @ Z
0
1
1.0V @ 50
0.7V @ 50
IDT
TM
Frequency Generator with 133MHz Differential CPU Clocks
0601G—01/26/10
3
ICS932S203
Frequency Generator with 133MHz Differential CPU Clocks
Byte 0: Control Register
Bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Pin#
-
55
40
34
-
35
-
-
Name
FS0
FS1
PCI_STOP#
3
PWD
1
X
X
X
1
Type
R
R
R
Description
(Reserved)
Reflects the value of FS0 pin sampled on power up
Reflects the value of FS1 pin sampled on power up
Hardware mode: Reflects the value of PCI_STOP#
pin sampled on PWD
(Reserved)
VCH Select 66MHz/48MHz
0=66MHz, 1=48MHz
(Reserved)
0=Spread Off, 1=Spread On
3V66_1/VCH
Spread
Enabled
0
0
0
RW
RW
Byte 1: Control Register
Bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Pin#
52, 51
49, 48
45, 44
52, 51
49, 48
45, 44
53, 54
43
Name
CPUCLKT0
CPUCLKC0
CPUCLKT1
CPUCLKC1
CPUCLKT2
CPUCLKC2
PWD
1
1
1
0
0
0
Type
RW
RW
RW
-
-
-
RW
R
Description
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
Reser ved
Reser ved
Reser ved
0=Disabled 1=Enabled
Reflects the current value of MULTSEL0
CPUCLKT3
CPUCLKC3
MULTSEL0
1
X
Notes:
1. R= Read only RW= Read and Write
2. PWD = Power on Default
3. The purpose of this bit is to allow a system designer to implement PCI_STOP functionality in one of two ways. Wither the
system designer can choose to use the externally provided PCI_STOP# pin to assert and de-assert PCI_STOP
functionality via SMBus Byte 0 Bit 3.
In Hardware mode it is not allowed to write to the SMBus Byte 0 Bit3. In Software mode it is not allowed to pull the
external PCI_STOP pin low. This avoids the issues related with Hardware started and software stopped PCI_STOP
conditions. The clock chip is to be operated in the Hardware or Software PCI_STOP mode ONLY, it is not allowed to mix
these modes.
In Hardware mode the SMBus byte 0 Bit 3 is R/W and should reflect the status of the part. Whether or not the chip is in
PCI_STOP mode.
Functionality PCI_STOP mode should be entered when [(PCI_STOP#=0) or (SMBus Byte 0 Bit 3 = 0)].
IDT
TM
Frequency Generator with 133MHz Differential CPU Clocks
0601G—01/26/10
4
ICS932S203
Frequency Generator with 133MHz Differential CPU Clocks
Byte 2: Control Register
Bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Pin#
10
11
12
13
16
17
18
-
Name
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCICLK6
-
PWD
1
1
1
1
1
1
1
0
Type
RW
RW
RW
RW
RW
RW
RW
-
Description
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
(Reserved)
Byte 3: Control Register
Bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Pin#
5
6
7
5
6
7
39
38
Name
PCICLK_F0
PCICLK_F1
PCICLK_F2
PCICLK_F0
PCICLK_F1
PCICLK_F2
48MHz_USB
48MHz_DOT
PWD
1
1
1
0
0
0
1
1
Type
RW
RW
RW
RW
RW
RW
RW
RW
Description
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
Allow control of PCICLK_F0 with asser tion of
PCI_STOP#. 0=Free Running, 1=Not free running
Allow control of PCICLK_F1 with asser tion of
PCI_STOP#. 0=Free Running, 1=Not free running
Allow control of PCICLK_F2 with asser tion of
PCI_STOP#. 0=Free Running, 1=Not free running
0=Disabled 1=Enabled
0=Disabled 1=Enabled
Byte 4: Control Register
Bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Pin#
21
22
23
24
35
33
-
-
Name
66MHz_OUT0/3V66-2
66MHz_OUT0/3V66-3
66MHz_OUT0/3V66-4
3V66_5
3V66_1/VCH_CLK
3V66_0
-
-
PWD
1
1
1
1
1
1
0
0
Type
RW
RW
RW
RW
RW
RW
R
R
Description
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
(Reserved)
(Reserved)
Notes:
1. R= Read only RW= Read and Write
2. PWD = Power on Default
IDT
TM
Frequency Generator with 133MHz Differential CPU Clocks
0601G—01/26/10
5
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