CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
2. Short circuit may be applied to ground or to either supply.
Electrical Specifications
T
A
= 25
o
C, V+ = 5V, V- = 0V, Unless Otherwise Specified
TEST
CONDITIONS
V
O
= 2.5V
V
O
= 2.5V
V
O
= 2.5V
V
CM
= 0 to 1V
V
CM
= 0 to 2.5V
CA5160
MIN
-
-
-
70
60
2.5
-
∆V+
= 1V;
∆V-
= 1V
R
L
=
∞
R
L
=10kΩ
I
SOURCE
I
SINK
V
OUT
V
O
= 0V
V
O
= 5V
R
L
=
∞
55
95
85
1.0
1.0
4.99
-
R
L
= 10kΩ
4.4
-
R
L
= 2kΩ
2.5
-
I
SUPPLY
I
SUPPLY
V
O
= 0V
V
O
= 2.5V
-
-
TYP
2
0.1
2
80
69
2.8
-0.5
67
117
102
3.4
2.2
5
0
4.7
0
3.3
0
50
320
MAX
10
10
15
-
-
-
0
-
-
-
4.0
4.0
-
0.01
-
0.01
-
0.01
100
400
UNITS
mV
pA
pA
dB
dB
V
V
dB
dB
dB
mA
mA
V
V
V
V
V
V
µA
µA
PARAMETER
Input Offset Voltage
Input Offset Current
Input Current
Common Mode Rejection Ratio
SYMBOL
V
IO
I
IO
I
I
CMRR
Common Mode Input Voltage Range
V
lCR
+
V
lCR
-
Power Supply Rejection Ratio
Large Signal Voltage
Gain (Note 3)
Source Current
Sink Current
Maximum Output Voltage V
OM
+
V
OM
-
V
OM
+
V
OM
-
V
OM
+
V
OM
-
Supply Current
V
O
= 0.1 to 4.1V
V
O
= 0.1 to 3.6V
PSRR
A
OL
NOTE:
3. For V+ = 4.5V and V- = GND; V
OUT
= 0.5V to 3.2V at R
L
= 10kΩ.
Electrical Specifications
T
A
= -55
o
C to 125
o
C, V+ = 5V, V- = 0V, Unless Otherwise Specified
TEST
CONDITIONS
V
O
= 2.5V
V
O
= 2.5 V
CA5160
MIN
-
-
TYP
3
0.1
MAX
15
10
UNITS
mV
nA
PARAMETER
Input Offset Voltage
Input Offset Current
SYMBOL
V
IO
I
IO
3-2
CA5160
Electrical Specifications
T
A
= -55
o
C to 125
o
C, V+ = 5V, V- = 0V, Unless Otherwise Specified
(Continued)
TEST
CONDITIONS
V
O
= 2.5V
V
CM
= 0 to 1V
V
CM
= 0 to 2.5V
Common Mode Input Voltage Range
V
lCR
+
V
lCR
-
Power Supply Rejection Ratio
Large Signal Voltage Gain
(Note 4)
Source Current
Sink Current
Maximum Output Voltage
V
OM
+
V
OM
-
V
OM
+
V
OM
-
V
OM
+
V
OM
-
Supply Current
V
O
= 0V
V
O
= 2.5V
NOTE:
4. For V+ = 4.5V and V- = GND; V
OUT
= 0.5V to 3.2V at R
L
= 10kΩ.
I
SUPPLY
I
SUPPLY
R
L
= 2kΩ
R
L
= 10kΩ
V
O
= 0.1 to 4.1V
V
O
= 0.1 to 3.6V
I
SOURCE
I
SINK
V
OUT
PSRR
A
OL
∆V+
= 2V
R
L
=
∞
R
L
=10kΩ
V
O
= 0V
V
O
= 5V
R
L
=
∞
CA5160
MIN
-
60
50
2.5
-
40
90
75
0.6
0.6
4.99
-
4.0
-
2.0
-
-
-
TYP
2
80
75
2.8
-0.5
60
110
100
-
-
5
0
4.3
0
2.5
0
170
410
MAX
15
-
-
-
0
-
-
-
5.0
5.0
-
0.01
-
0.01
-
0.01
220
500
UNITS
nA
dB
dB
V
V
dB
dB
dB
mA
mA
V
V
V
V
V
V
µA
µA
PARAMETER
Input Current
Common Mode Rejection Ratio
SYMBOL
I
I
CMRR
Electrical Specifications
T
A
= 25
o
C, V+ = 15V, V- = 0V, Unless Otherwise Specified
TEST
CONDITIONS
V
S
=
±7.5V
V
S
=
±7.5V
V
S
=
±7.5V
V
O
= 10V
P-P
R
L
= 2kΩ
CA5160
MIN
-
-
-
50
94
70
10
∆V+
= 1V;
∆V-
= 1V
V
S
=
±7.5V
R
L
= 2kΩ
-
12
-
R
L
=
∞
14.99
-
TYP
6
0.5
5
320
110
90
-0.5 to 12
32
13.3
0.002
15
0
MAX
15
30
50
-
-
-
0
320
-
0.01
-
0.1
UNITS
mV
pA
pA
kV/V
dB
dB
V
µV/V
V
V
V
V
PARAMETER
Input Offset Voltage
Input Offset Current
Input Current
Large Signal Voltage Gain
SYMBOL
V
IO
I
IO
I
I
A
OL
Common Mode Rejection Ratio
Common Mode Input Voltage Range
Power Supply Rejection Ratio
Maximum Output
Voltage
V
OM
+
V
OM
-
V
OM
+
V
OM
-
CMRR
V
lCR
PSRR
V
OUT
3-3
CA5160
Electrical Specifications
T
A
= 25
o
C, V+ = 15V, V- = 0V, Unless Otherwise Specified
(Continued)
TEST
CONDITIONS
V
O
= 0V
V
O
= 15V
I+
R
L
=
∞
, V
O
= 7.5V
R
L
=
∞
, V
O
= 0V
Input Offset Voltage Temperature Drift
∆V
IO
/∆T
CA5160
MIN
12
12
-
-
-
TYP
22
20
10
2
8
MAX
45
45
15
3
-
UNITS
mA
mA
mA
mA
µV/
o
C
PARAMETER
Maximum Output
Current
Supply Current
I
OM
+ (Source)
I
OM
- (Sink)
SYMBOL
I
O
Electrical Specifications
For Design Guidance, At T
A
= 25
o
C, V
SUPPLY
=
±7.5V,
Unless Otherwise Specified
TYPICAL
VALUES
PARAMETER
Input Offset Voltage Adjustment Range
Input Resistance
Input Capacitance
Equivalent Input Noise Voltage
SYMBOL
TEST CONDITIONS
10kΩ Across Terminals 4 and 5 or 4 and 1
CA5160
±22
1.5
UNITS
mV
TΩ
pF
µV
µV
nV/√Hz
nV/√Hz
MHz
V/µs
µs
%
µs
R
I
C
I
e
N
f = 1MHz
BW = 0.2MHz, R
S
= 1MΩ
BW = 0.2MHz, R
S
= 10MΩ
4.3
40
50
72
30
4
10
Equivalent Input Noise Voltage
e
N
R
S
= 100Ω, 1kHz
R
S
= 100Ω, 10kHz
Unity Gain Crossover Frequency
Slew Rate
Transient Response
Rise Time
Overshoot
Settling Time (To <0.1%, V
IN
= 4V
P-P
)
f
T
SR
t
R
OS
t
S
C
C
= 25pF, R
L
= 2kΩ, (Voltage Follower)
C
C
= 25pF, R
L
= 2kΩ (Voltage Follower)
0.09
10
1.8
Block Diagram
7
200µA
1.35mA
200µA
8mA
(NOTE 5)
0mA
(NOTE 6)
V+
BIAS CKT.
NOTE:
5. Total supply voltage (for indicated voltage
gains) = 15V with input terminals biased so
that Terminal 6 potential is +7.5V above
Terminal 4.
6. Total supply voltage (for indicated voltage
gains) = 15V with output terminal driven to
either supply rail.
+
3
INPUT
2
A
V
≈
5X
A
V
≈
6000X
A
V
≈
30X
OUTPUT
6
-
4
C
C
COMPENSATION
(WHEN DESIRED)
V-
5
1
8
STROBE
OFFSET
NULL
3-4
CA5160
Schematic Diagram
BIAS CIRCUIT
CURRENT SOURCE
FOR Q
6
AND Q
7
“CURRENT SOURCE
LOAD” FOR Q
11
7
V+
Q
1
D
1
Z
1
8.3V
R
1
40kΩ
R
2
5kΩ
INPUT STAGE
D
5
NON-INV.
INPUT
3
2
+
D
2
D
3
D
4
Q
2
Q
3
Q
4
Q
5
D
6
D
7
SECOND
STAGE
OUTPUT
STAGE
Q
8
OUTPUT
6
Q
6
Q
7
2kΩ
R
4
1kΩ
Q
10
30
pF
Q
12
-
R
3
1kΩ
Q
9
INV. INPUT
Q
11
R
5
1kΩ
R
6
1kΩ
SUPPLEMENTARY
COMP IF DESIRED
5
OFFSET NULL
1
8
STROBING
4
NOTE: Diodes D
5
through D
7
provide gate oxide protection for MOSFET Input Stage.
Application Information
Circuit Description
Refer to the block diagram of the CA5160 CMOS Operational
Amplifier. The input terminals may be operated down to 0.5V
below the negative supply rail, and the output can be swung
very close to either supply rail in many applications. Conse-
quently, the CA5160 circuit is ideal for single supply operation.
Three class A amplifier stages, having the individual gain
capability and current consumption shown in the block dia-
gram, provide the total gain of the CA5160. A biasing circuit
provides two potentials for common use in the first and sec-
ond stages. Terminals 8 and 1 can be used to supplement the
internal phase compensation network if additional phase com-
pensation or frequency roll-off is desired. Terminals 8 and 4
can also be used to strobe the output stage into a low quies-
cent current state. When Terminal 8 is tied to the negative
supply rail (Terminal 4) by mechanical or electrical means, the
output potential at Terminal 6 essentially rises to the positive
supply rail potential at Terminal 7. This condition of essentially
zero current drain in the output stage under the strobed “OFF”
condition can only be achieved when the ohmic load resis-
tance presented to the amplifier is very high (e.g., when the
amplifier output is used to drive CMOS digital circuits in com-
parator applications).
Input Stages
The circuit of the CA5160 is shown in the schematic diagram.
It consists of a differential input stage using PMOS field effect
transistors (Q
6
, Q
7
) working into a mirror pair of bipolar tran-
sistors (Q
9
, Q
10
) functioning as load resistors together with
resistors R
3
through R
6
. The mirror pair transistors also func-
tion as a differential-to-single-ended converter to provide base
drive to the second-stage bipolar transistor (Q
11
). Offset null-
ing, when desired, can be effected by connecting a 100,000Ω
potentiometer across Terminals 1 and 5 and the potentiome-
ter slider arm to Terminal 4.
Cascode-connected PMOS transistors Q
2
, Q
4
, are the
constant current source for the input stage. The biasing
circuit for the constant current source is subsequently
described. The small diodes D
5
through D
7
provide gate-
oxide protection against high voltage transients, including
static electricity during handling for Q
6
and Q
7
.
Second Stage
Most of the voltage gain in the CA5160 is provided by the
second amplifier stage, consisting of bipolar transistor Q
11
and its cascode-connected load resistance provided by
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