TC55VZM208AJGN/ATGN08,10,12
TENTATIVE
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
524,288-WORD BY 8-BIT CMOS STATIC RAM
DESCRIPTION
The TC55VZM208AJGN/ATGN is a 4,194,304-bit high-speed static random access memory (SRAM) organized as
524,288 words by 8 bits. Fabricated using CMOS technology and advanced circuit techniques to provide high speed,
it operates from a single 3.3 V power supply. Chip enable ( CE ) can be used to place the device in a low-power mode,
and output enable ( OE ) provides fast memory access. This device is well suited to cache memory applications
where high-speed access and high-speed storage are required. All inputs and outputs are directly LVTTL
compatible. The TC55VZM208AJGN/ATGN is available in plastic 36-pin SOJ and 44-pin TSOP with 400mil width
for high density surface assembly.
FEATURES
•
Fast access time (the following are maximum values)
TC55VZM208AJGN/ATGN08:8 ns
TC55VZM208AJGN/ATGN10:10 ns
TC55VZM208AJGN/ATGN12:12 ns
Low-power dissipation
(the following are maximum values)
Cycle Time
Operation (max)
8
100
10
80
12
70
ns
mA
•
•
•
•
•
•
Single power supply voltage of 3.3 V
±
0.3 V
Fully static operation
All inputs and outputs are LVTTL compatible
Output buffer control using OE
Package:
SOJ36-P-400-1.27 (AJGN)
(Weight: 1.35 g typ)
TSOP II44-P-400-0.80 (ATGN) (Weight: 0.45 g typ)
Standby:4 mA (both devices)
PIN ASSIGNMENT
(TOP VIEW)
36 PIN SOJ
44 PIN TSOP
PIN NAMES
A0 to A18
NC
NC
A17
A3
A2
A1
A0
CE
I/O1
I/O2
V
DD
GND
I/O3
I/O4
WE
A16
A15
A14
A13
A18
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
A4
A5
A6
A7
OE
I/O8
I/O7
GND
V
DD
I/O6
I/O5
A8
A9
A10
A11
A12
NU
NC
NC
I/O1 to I/O8
CE
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Write Enable Input
Output Enable Input
Power (+3.3 V)
Ground
No Connection
Not Usable (Input)
A17
A3
A2
A1
A0
CE
I/O1
I/O2
V
DD
GND
I/O3
I/O4
WE
A16
A15
A14
A13
A18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
A4
A5
A6
A7
OE
I/O8
I/O7
GND
V
DD
I/O6
I/O5
A8
A9
A10
A11
A12
NU
WE
OE
V
DD
GND
NC
NU
(TC55VZM208AJGN)
(TC55VZM208ATGN)
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TC55VZM208AJGN/ATGN08,10,12
BLOCK DIAGRAM
A0
A1
A4
A8
A9
A12
A14
A15
A16
A17
ROW ADDRESS
BUFFER
V
DD
GND
ROW
DECODER
MEMORY CELL ARRAY
512
×
1,024
×
8
(4,194,304)
CE
I/O1
I/O2
I/O3
I/O4
I/O5
I/O5
I/O7
I/O8
DATA OUTPUT
BUFFER
CE
COLUMN ADDRESS BUFFER
CLOCK
GENERATOR
A2 A3 A5 A6 A7 A10 A11A13 A18
VALUE
−0.5
to 4.6
−0.5*
to 4.6
−0.5*
to V
DD
+
0.5**
1.4
−65
to 150
−10
to 85
DATA INPUT
BUFFER
SENSE AMP
COLUMN DECODER
WE
OE
CE
CE
MAXIMUM RATINGS
SYMBOL
V
DD
V
IN
V
I/O
P
D
T
stg
T
opr
Power Supply Voltage
Input Terminal Voltage
Input/Output Terminal Voltage
Power Dissipation
Storage Temperature
Operating Temperature
RATING
UNIT
V
V
V
W
°C
°C
*:
−1.5
V with a pulse width of 20%½t
RC
min (4 ns max)
**:
V
DD
+
1.5 V with a pulse width of 20%½t
RC
min (4 ns max)
DC RECOMMENDED OPERATING CONDITIONS
(Ta
=
0° to 70°C)
SYMBOL
V
DD
V
IH
V
IL
PARAMETER
Power Supply Voltage
Input High Voltage
Input Low Voltage
MIN
3.0
2.0
−0.3*
TYP
3.3
MAX
3.6
V
DD
+
0.3**
0.8
UNIT
V
V
V
*:
−1.0
V with a pulse width of 20%½t
RC
min (4 ns max)
**:
V
DD
+
1.0 V with a pulse width of 20%½t
RC
min (4 ns max)
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TC55VZM208AJGN/ATGN08,10,12
DC CHARACTERISTICS
(Ta
=
0° to 70°C, V
DD
=
3.3 V
±
0.3 V)
SYMBOL
I
IL
I
LO
I
I (NU)
PARAMETER
Input Leakage Current
V
IN
=
0 to V
DD
(Except NU pin)
Output Leakage
Current
CE
=
V
IH
or WE
=
V
IL
or
OE
=
V
IH
,
V
OUT
=
0 to V
DD
TEST CONDITION
MIN
−1
−1
−1
2.4
V
DD
−
0.2
t
cycle
=
8 ns
t
cycle
=
10 ns
t
cycle
=
12 ns
TYP
MAX
1
UNIT
µA
µA
µA
1
Input Leakage Current
V
IN
=
0 V
(NU pin)
Output High Voltage
I
OH
= −2
mA
I
OH
= −100 µA
I
OL
=
2 mA
I
OL
=
100
µA
CE
=
V
IL
, I
OUT
=
0 mA,
1
0.4
0.2
100
80
70
30
V
OH
V
V
OL
Output Low Voltage
I
DDO
Operating Current
OE
=
V
IH
,
mA
Other Input
=
V
IH
/V
IL
I
DDS1
I
DDS2
CE
=
V
IH
, Other Input
=
V
IH
or V
IL
Standby Current
CE
=
V
DD
−
0.2 V, Other Input
=
V
DD
−
0.2 V or 0.2 V
mA
4
CAPACITANCE
(Ta
=
25°C, f
=
1 .0 MHz)
SYMBOL
C
IN
C
I/O
Note:
PARAMETER
Input Capacitance
Input/Output Capacitance
V
IN
=
GND
V
I/O
=
GND
TEST CONDITION
MAX
6
8
UNIT
pF
pF
This parameter is periodically sampled and is not 100% tested.
OPERATING MODE
MODE
Read
Write
Outputs Disable
Standby
*
: Don’t care
Note:
The NU pin must be left unconnected or tied to GND.
You must not apply a voltage of more than 0.8 V to the NU.
CE
OE
WE
H
L
H
*
Output
Input
I/O1 to I/O8
POWER
I
DDO
I
DDO
I
DDO
I
DDS
L
L
L
H
L
*
H
*
High Impedance
High Impedance
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TC55VZM208AJGN/ATGN08,10,12
AC CHARACTERISTICS
(Ta
=
0° to 70°C
READ CYCLE
TC55VZM208AJGN/ATGN
SYMBOL
PARAMETER
MIN
t
RC
t
ACC
t
CO
t
OE
t
OH
t
COE
t
OEE
t
COD
t
ODO
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Output Data Hold Time from Address Change
Output Enable Time from Chip Enable
Output Enable Time from Output Enable
Output Disable Time from Chip Enable
Output Disable Time from Output Enable
8
3
3
0
08
MAX
8
8
4
4
4
MIN
10
3
3
0
10
MAX
10
10
5
5
5
MIN
12
3
3
0
12
MAX
12
12
6
6
6
ns
UNIT
(See Note 1)
, V
DD
=
3.3 V
±
0.3 V)
WRITE CYCLE
TC55VZM208AJGN/ATGN
SYMBOL
PARAMETER
MIN
t
WC
t
WP
t
CW
t
AW
t
AS
t
WR
t
DS
t
DH
t
OEW
t
ODW
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Address Valid to End of Write
Address Setup Time
Write Recovery Time
Data Setup Time
Data Hold Time
Output Enable Time from Write Enable
Output Disable Time from Write Enable
8
6
6
6
0
0
4
0
3
08
MAX
4
MIN
10
7
7
7
0
0
5
0
3
10
MAX
5
MIN
12
8
8
8
0
0
6
0
3
12
MAX
6
ns
UNIT
AC TEST CONDITIONS
PARAMETER
Input Pulse Level
Input Pulse Rise and Fall Time
Input Timing Measurement
Reference Level
Output Timing Measurement
Reference Level
Output Load
TEST CONDITION
3.0 V/ 0.0 V
2 ns
1.5 V
Fig.1
3.3 V
1200
Ω
I/O pin
R
L
=
50
Ω
V
L
=
1.5 V
1.5 V
Fig.1
870
Ω
I/O pin Z
0
=
50
Ω
C
L
=
30 pF
C
L
=
5 pF
(For t
COE
, t
OEE
, t
COD
,
t
ODO
, t
OEW
and t
ODW
)
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TC55VZM208AJGN/ATGN08,10,12
TIMING DIAGRAMS
READ CYCLE
(See Note 2)
t
RC
Address
t
ACC
t
CO
CE
t
OH
t
OE
OE
t
COD
(See Note 6)
t
OEE
t
COE
D
OUT
Hi-Z
(See Note 6)
(See Note 6)
t
ODO
(See Note 6)
VALID DATA OUT
INDETERMINATE
Hi-Z
INDETERMINATE
WRITE CYCLE 1 ( WE CONTROLLED)
(See Note 5)
t
WC
t
AW
Address
t
AS
WE
t
CW
CE
t
WP
t
WR
t
ODW
D
OUT
(See Note 3)
INDETERMINATE
(See Note 6)
t
OEW
(See Note 6)
Hi-Z
t
DS
t
DH
(See Note 4)
INDETERMINATE
D
IN
VALID DATA IN
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