Freescale Semiconductor, Inc.
TECHNICAL DATA
Order number: MPC92459
Rev 0, 08/2004
Preliminary Information
900 MHz Low Voltage LVDS Clock
Synthesizer
The MPC92459 is a 3.3 V compatible, PLL based clock synthesizer targeted
for high performance clock generation in mid-range to high-performance
telecom, networking and computing applications. With output frequencies from
50 MHz to 900 MHz and the support of differential LVDS output signals the
device meets the needs of the most demanding clock applications.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
50 MHz to 900 MHz synthesized clock output signal
Differential LVDS output
LVCMOS compatible control inputs
On-chip crystal oscillator for reference frequency generation
Alternative LVCMOS compatible reference input
3.3 V power supply
Fully integrated PLL
Minimal frequency overshoot
Serial 3-wire programming interface
Parallel programming interface for power-up
32 Pin LQFP Package
SiGe Technology
Ambient temperature range 0°C to + 70°C
MPC92459
900 MHz LOW VOLTAGE
CLOCK SYNTHESIZER
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-03
Functional Description
The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. The frequency of the internal
crystal oscillator or external reference clock signal is multiplied by the PLL. The VCO within the PLL operates over a range of 800 to
1800 MHz. Its output is scaled by a divider that is configured by either the serial or parallel interfaces. The crystal oscillator frequency
f
XTAL
, the PLL feedback-divider M and the PLL post-divider N determine the output frequency.
The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to be M times the reference frequency by
adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve phase lock. The
PLL will be stable if the VCO frequency is within the specified VCO frequency range (800 to 1800 MHz). The M-value must be pro-
grammed by the serial or parallel interface.
The PLL post-divider N is configured through either the serial or the parallel interfaces, and can provide one of four division ratios
(1, 2, 4, or 8). This divider extends performance of the part while providing a 50% duty cycle.
The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[6:0] and N[1:0] inputs
to configure the internal counters. It is recommended on system reset to hold the P_LOAD input LOW until power becomes valid. On
the LOW-to-HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the serial interface.
Internal pullup resistors are provided on the M[6:0] and N[1:0] inputs prevent the LVCMOS compatible control inputs from floating.
The serial interface centers on a twelve bit shift register. The shift register shifts once per rising edge of the S_CLOCK input. The serial
input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The configuration
latches will capture the value of the shift register on the HIGH-to-LOW edge of the S_LOAD input. See
PROGRAMMING INTERFACE
for more information. The TEST output reflects various internal node values, and is controlled by the T[2:0] bits in the serial data
stream. In order to minimize the PLL jitter, it is recommended to avoid active signal on the TEST output. The PWR_DOWN pin, when
asserted, will synchronously divide the f
OUT
by 16. The power down sequence is clocked by the PLL reference clock, thereby causing
the frequency reduction to happen relatively slowly. Upon de-assertion of the PWR_DOWN pin, the f
OUT
input will step back up to its
programmed frequency in four discrete increments.
This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
453
MPC92459
XTAL_IN
XTAL_OUT
f
REF_EXT
V
CC
XTAL_SEL
V
CC
P_LOAD
S_LOAD
LE
P/S
0
S_DATA
S_CLOCK
BITS 11-5
V
CC
1
BITS 3-4
12-BIT SHIFT REGISTER
0
1
BITS 0-2
XTAL
10 – 20 MHz
1
÷
2
0
Ref
VCO
÷
2
PLL
800 – 1800 MHz
FB
÷
0 TO
÷
127
7-BIT M-DIVIDER
9
M-LATCH
÷
2
÷
1
÷
2
÷
4
÷
8
11
00
01
10
÷
16
1
OE
0
f
OUT
f
OUT
TEST
2
N-LATCH
3
T-LATCH
TEST
M[0:6]
N[1:0]
PWR_DOWN
OE
Figure 1. MPC92459 Logic Diagram
XTAL_SEL
M[6]
M[5]
18
24
GND
TEST
V
CC
V
CC
GND
f
OUT
f
OUT
V
CC
25
26
27
28
29
30
31
32
1
23
22
21
20
19
M[4]
17
16
15
14
NC
M[3]
M[2]
M[1]
M[0]
P_LOAD
OE
XTAL_OUT
13
12
11
10
9
8
XTAL_IN
N[1]
N[0]
3
NC
MPC92459
2
NC
4
5
6
7
S_CLOCK
S_DATA
S_LOAD
Figure 2. MPC92459 32-Lead LQFP Pinout
(Top View)
454
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
PWR_DOWN
f
REF_EXT
V
CC_PLL
V
CC_PLL
MPC92459
Table 1. Pin Configurations
Pin
XTAL_IN, XTAL_OUT
f
REF_EXT
f
OUT
, f
OUT
TEST
XTAL_SEL
PWR_DOWN
Input
Output
Output
Input
Input
1
0
0
I/O
Default
Type
Analog
Crystal oscillator interface
Function
LVCMOS Alternative PLL reference input
LVDS
Differential clock output
LVCMOS Test and device diagnosis output
LVCMOS PLL reference select input
LVCMOS Configuration input for power down mode. Assertion (deassertion) of power down will
decrease (increase) the output frequency by a ratio of 16 in 4 discrete steps.
PWR_DOWN assertion (deassertion) is synchronous to the input reference clock.
LVCMOS Serial configuration control input. This inputs controls the loading of the configuration
latches with the contents of the shift register. The latches will be transparent when this
signal is high, thus the data must be stable on the high-to-low transition.
LVCMOS Parallel configuration control input. this input controls the loading of the configuration
latches with the content of the parallel inputs (M and N). The latches will be
transparent when this signal is low, thus the parallel data must be stable on the
low-to-high transition of P_LOAD. P_LOAD is state sensitive.
LVCMOS Serial configuration data input.
LVCMOS Serial configuration clock input.
LVCMOS Parallel configuration for PLL feedback divider (M).
M is sampled on the low-to-high transition of P_LOAD.
LVCMOS Parallel configuration for Post-PLL divider (N).
N is sampled on the low-to-high transition of P_LOAD
LVCMOS Output enable (active high)
The output enable is synchronous to the output clock to eliminate the possibility of runt
pulses on the f
OUT
output. OE = L low stops f
OUT
in the logic low state
(f
OUT
= L, f
OUT
= H).
Ground
V
CC
V
CC
Negative power supply (GND).
Positive power supply for I/O and core. All V
CC
pins must be connected to the positive
power supply for correct operation.
PLL positive power supply (analog power supply).
S_LOAD
Input
0
P_LOAD
Input
1
S_DATA
S_CLOCK
M[0:6]
N[1:0]
OE
Input
Input
Input
Input
Input
0
0
1
1
1
GND
V
CC
V
CC_PLL
Supply
Supply
Supply
Table 2. Output Frequency Range and PLL Post-Divider N
N
PWR_DOWN
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
VCO Output
Frequency Division
2
4
8
1
32
64
128
f
OUT
Frequency Range
200 – 450 MHz
100 – 225 MHz
50 – 112.5 MHz
400 – 900 MHz
12.5 – 28.125 MHz
6.25 – 14.0625 MHz
3.125 – 7.03125 MHz
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
455
MPC92459
Table 3. Function Table
Input
XTAL_SEL
OE
PWR_DOWN
0
FREF_EXT
Outputs disabled. f
OUT
is stopped in the logic low state (f
OUT
= L, f
OUT
= H)
Output divider
÷
1
1
XTAL interface
Outputs enabled
Output divider
÷
16
Table 4. General Specifications
Symbol
MM
HBM
LU
C
IN
Characteristics
ESD Protection (Machine model)
ESD Protection (Human body model)
Latch-up Immunity
Input Capacitance
Min
200
2000
200
4.0
Typ
Max
Unit
V
V
mA
pF
Inputs
Condition
Table 5. Absolute Maximum Ratings
1
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
T
S
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
Storage temperature
–65
Characteristics
Min
–0.3
–0.3
–0.3
Max
3.9
V
CC
+ 0.3
V
CC
+ 0.3
±20
±50
125
Unit
V
V
V
mA
mA
°C
Condition
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions
or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not
implied.
456
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
MPC92459
Table 6. DC Characteristics
(V
CC
= 3.3 V ± 5%, T
A
= 0°C to +70°C)
1
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
LVCMOS Control Inputs (f
REF_EXT
, PWR_DOWN, XTAL_SEL, P_LOAD, S_LOAD, S_DATA, S_CLOCK, M[0:6], N[0:1], OE)
V
IH
V
IL
I
IN
Input High Voltage
Input Low Voltage
Input Current
2
2.0
V
CC
+ 0.3
0.8
±200
V
V
µA
LVCMOS
LVCMOS
V
IN
= V
CC
or GND
Differential Clock Output f
OUT
V
PP
V
OS
Output Differential Voltage (peak-to-peak)
Output Offset Voltage
250
1125
1275
mV
mV
LVDS
LVDS
Test and Diagnosis Output TEST
V
OH
V
OL
Output High Voltage
Output Low Voltage
2.0
0.55
V
V
I
OH
=–0.8 mA
I
OL
= 0.8 mA
Supply Current
I
CC_PLL
I
CC
Maximum PLL Supply Current
Maximum Supply Current
20
110
mA
mA
V
CC_PLL
Pins
All V
CC
Pins
1. All AC characteristics are design targets and subject to change upon device characterization.
2. Inputs have pull-down resistors affecting the input current.
Table 7. AC Characteristics
(V
CC
= 3.3 V ± 5%, T
A
= 0°C to +70°C)
1
Symbol
f
XTAL
f
VCO
f
MAX
Characteristics
Crystal Interface Frequency Range
VCO Frequency Range
2
Output Frequency
N = 11 (÷ 1)
N = 00 (÷ 2)
N = 01 (÷ 4)
N = 10 (÷ 8)
Min
10
800
400
200
100
50
0
50
45
0.05
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to P_LOAD
S_DATA to S_CLOCK
M, N to P_LOAD
RMS (1
σ)
4
RMS (1
σ)
20
20
20
20
20
TBD
TBD
±25
10
50
55
TBD
Typ
Max
20
1800
900
450
225
112.5
10
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ns
%
ns
ns
ns
ns
ns
ns
ps
ps
ms
20% to 80%
PWR_DOWN = 0
Condition
f
S_CLOCK
t
P,MIN
DC
t
r
, t
f
t
S
Serial Interface Programming Clock Frequency
3
Minimum Pulse Width
Output Duty Cycle
Output Rise/Fall Time
Setup Time
(S_LOAD, P_LOAD)
t
S
t
JIT(CC)
t
JIT(PER)
t
LOCK
Hold Time
Cycle-to-Cycle Jitter
Period Jitter
Maximum PLL Lock Time
1. All AC characteristics are design targets and subject to change upon device characterization.
2. The input frequency f
XTAL
and the PLL feedback divider M must match the VCO frequency range: f
VCO
= f
XTAL
⋅
2
⋅
M.
3. The frequency of S_CLOCK is limited to 10 MHz in serial programming mode. S_CLOCK can be switched at higher frequencies when used as
test clock in test mode 6. See
APPLICATIONS INFORMATION
for more details.
4. Refer to the application section for a jitter calculation for other confidence factors than 1
σ.
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
457
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