EPM240F256C3 datasheet, PDF - EEWORLD Datasheet

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EPM240F256C3: DescriptionFLASH PLD, PBGA256; Categorysemiconductor Programmable logic devices; File Size72KB，6 Pages; ManufacturerAltera (Intel)

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EPM240F256C3 Overview

FLASH PLD, PBGA256

EPM240F256C3 Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	256
Maximum operating temperature	85 Cel
Minimum operating temperature	0.0 Cel
Maximum supply/operating voltage	2.62 V
Minimum supply/operating voltage	2.38 V
Rated supply voltage	2.5 V
Number of input and output buses	212
Processing package description	17 × 17 MM, 1 MM PITCH, LEAD FREE, FBGA-256
Lead-free	Yes
EU RoHS regulations	Yes
China RoHS regulations	Yes
state	ACTIVE
Craftsmanship	CMOS
packaging shape	SQUARE
Package Size	GRID array
surface mount	Yes
Terminal form	BALL
Terminal spacing	1 mm
terminal coating	tin silver copper
Terminal location	BOTTOM
Packaging Materials	Plastic/Epoxy
Temperature level	other
organize	0 DEDICATED INPUTS, 212 I/O
Output function	MACROCELL
Programmable logic type	flash programmable logic device
Dedicated input quantity	0.0

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1. Introduction

MII51001-1.9

Introduction

The MAX

II family of instant-on, non-volatile CPLDs is based on a 0.18-µm,

6-layer-metal-flash process, with densities from 240 to 2,210 logic elements (LEs) (128

to 2,210 equivalent macrocells) and non-volatile storage of 8 Kbits. MAX II devices

offer high I/O counts, fast performance, and reliable fitting versus other CPLD

architectures. Featuring MultiVolt core, a user flash memory (UFM) block, and

enhanced in-system programmability (ISP), MAX II devices are designed to reduce

cost and power while providing programmable solutions for applications such as bus

bridging, I/O expansion, power-on reset (POR) and sequencing control, and device

configuration control.

Features

The MAX II CPLD has the following features:

■

Low-cost, low-power CPLD

Instant-on, non-volatile architecture

Standby current as low as 25 µA

Provides fast propagation delay and clock-to-output times

Provides four global clocks with two clocks available per logic array block (LAB)

UFM block up to 8 Kbits for non-volatile storage

MultiVolt core enabling external supply voltages to the device of either

3.3 V/2.5 V or 1.8 V

MultiVolt I/O interface supporting 3.3-V, 2.5-V, 1.8-V, and 1.5-V logic levels

Bus-friendly architecture including programmable slew rate, drive strength,

bus-hold, and programmable pull-up resistors

Schmitt triggers enabling noise tolerant inputs (programmable per pin)

I/Os are fully compliant with the Peripheral Component Interconnect Special

Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V

operation at 66 MHz

Supports hot-socketing

Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry

compliant with IEEE Std. 1149.1-1990

ISP circuitry compliant with IEEE Std. 1532

■

Altera Corporation

MAX II Device Handbook

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