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VSC8558
Octal 10/100/1000BASE-T PHY with
Dual 1.25 Gbps SerDes
Datasheet
VMDS-10201
Revision 4.0
June 2006
Downloaded by data_acq@partminer.com on May 5, 2008 from Vitesse.com
Vitesse
Corporate Headquarters
741 Calle Plano
Camarillo, California 93012
United States
www.vitesse.com
Copyright© 2005–2006 by Vitesse Semiconductor Corporation
Vitesse Semiconductor Corporation (“Vitesse”) retains the right to make changes to its
products or specifications to improve performance, reliability or manufacturability. All
information in this document, including descriptions of features, functions,
performance, technical specifications and availability, is subject to change without
notice at any time. While the information furnished herein is held to be accurate and
reliable, no responsibility will be assumed by Vitesse for its use. Furthermore, the
information contained herein does not convey to the purchaser of microelectronic
devices any license under the patent right of any manufacturer.
Vitesse products are not intended for use in life support products where failure of a
Vitesse product could reasonably be expected to result in death or personal injury.
Anyone using a Vitesse product in such an application without express written consent
of an officer of Vitesse does so at their own risk, and agrees to fully indemnify Vitesse
for any damages that may result from such use or sale.
Vitesse Semiconductor Corporation is a registered trademark. All other products or
service names used in this publication are for identification purposes only, and may be
trademarks or registered trademarks of their respective companies. All other
trademarks or registered trademarks mentioned herein are the property of their
respective holders.
June 2006
Page 2 of 108
VSC8558 Datasheet
Contents
Contents
Revision History ............................................................................. 10
1
2
Introduction ........................................................................... 14
Product Overview ................................................................... 15
2.1
2.2
Features and Benefits .......................................................................... 15
Block Diagram .................................................................................... 17
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3
Functional Descriptions .......................................................... 18
3.1
Operating Modes.................................................................................
3.1.1 SerDes MAC-to-Cat5 Mode MAC Interface.....................................
3.1.2 SGMII MAC-to-Cat5 Mode MAC Interface ......................................
3.1.3 All Modes Cat5 Media Interface ...................................................
SerDes Media Interface........................................................................
SGMII MAC-to-100BASE-FX Mode .........................................................
Automatic Media-Sense (AMS) Interface Mode ........................................
Cat5 Auto-Negotiation .........................................................................
Manual MDI/MDI-X Setting ...................................................................
Automatic Crossover and Polarity Detection ............................................
Link Speed Downshift ..........................................................................
Transformer-less Ethernet ....................................................................
Ethernet In-line Powered Devices ..........................................................
802.3af PoE Support ...........................................................................
ActiPHY Power Management .................................................................
3.12.1 Low Power State .......................................................................
3.12.2 Link Partner Wake-up State ........................................................
3.12.3 Normal Operating State .............................................................
Serial Management Interface ................................................................
3.13.1 SMI Frames..............................................................................
3.13.2 SMI Interrupts..........................................................................
LED Interface .....................................................................................
3.14.1 LED Modes ...............................................................................
3.14.2 LED Behavior............................................................................
3.14.3 Serial LED Mode........................................................................
GPIO Pins ..........................................................................................
Testing Features .................................................................................
3.16.1 Ethernet Packet Generator (EPG) ................................................
3.16.2 CRC Counters ...........................................................................
3.16.3 Far-end Loopback .....................................................................
3.16.4 Near-end Loopback ...................................................................
3.16.5 Connector Loopback ..................................................................
3.16.6 VeriPHY Cable Diagnostics ..........................................................
3.16.7 IEEE 1149.1 JTAG Boundary Scan ...............................................
3.16.8 JTAG Instruction Codes ..............................................................
3.16.9 Boundary Scan Register Cell Order ..............................................
IEEE 1149.6 AC-JTAG Boundary Scan Interface .......................................
18
19
20
21
21
22
22
24
24
25
25
26
26
28
28
29
29
30
30
30
31
32
33
34
34
35
36
36
36
37
37
37
38
39
40
41
41
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
3.13
3.14
3.15
3.16
3.17
June 2006
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VSC8558 Datasheet
Contents
4
Configuration ......................................................................... 42
4.1
4.2
Registers ...........................................................................................
4.1.1 Reserved Registers....................................................................
4.1.2 Reserved Bits ...........................................................................
IEEE Standard and Main Registers .........................................................
4.2.1 Mode Control............................................................................
4.2.2 Mode Status .............................................................................
4.2.3 Device Identification..................................................................
4.2.4 Auto-Negotiation Advertisement..................................................
4.2.5 Link Partner Auto-Negotiation Capability ......................................
4.2.6 Auto-Negotiation Expansion........................................................
4.2.7 Transmit Auto-Negotiation Next Page ...........................................
4.2.8 Auto-Negotiation Link Partner Next Page Receive...........................
4.2.9 1000BASE-T Control ..................................................................
4.2.10 1000BASE-T Status ...................................................................
4.2.11 Main Registers Reserved Addresses .............................................
4.2.12 1000BASE-T Status Extension 1 ..................................................
4.2.13 100BASE-TX Status Extension.....................................................
4.2.14 1000BASE-T Status Extension 2 ..................................................
4.2.15 Bypass Control .........................................................................
4.2.16 Reserved Address Space ............................................................
4.2.17 Extended Control and Status ......................................................
4.2.18 Extended PHY Control Set 1........................................................
4.2.19 Extended PHY Control Set 2........................................................
4.2.20 Interrupt Mask..........................................................................
4.2.21 Interrupt Status........................................................................
4.2.22 MAC Interface Auto-Negotiation Control and Status .......................
4.2.23 Device Auxiliary Control and Status .............................................
4.2.24 LED Mode Select .......................................................................
4.2.25 LED Behavior............................................................................
Extended Page Registers ......................................................................
4.3.1 Extended Page Access ...............................................................
4.3.2 SerDes Media Control ................................................................
4.3.3 SerDes MAC Control ..................................................................
4.3.4 CRC Good Counter ....................................................................
4.3.5 SIGDET Control ........................................................................
4.3.6 Extended PHY Control ................................................................
4.3.7 EEPROM Interface Status and Control ..........................................
4.3.8 EEPROM Data Read/Write...........................................................
4.3.9 PoE and Miscellaneous Functionality.............................................
4.3.10 VeriPHY Control 1......................................................................
4.3.11 VeriPHY Control 2......................................................................
4.3.12 VeriPHY Control 3......................................................................
4.3.13 Reserved Extended Registers ......................................................
4.3.14 Ethernet Packet Generator Control 1............................................
4.3.15 Ethernet Packet Generator Control 2............................................
General-Purpose I/O Registers ..............................................................
4.4.1 Reserved GPIO Registers............................................................
4.4.2 SIGDET Control Register ............................................................
4.4.3 GPIO Input Register ..................................................................
4.4.4 GPIO Output Register ................................................................
42
43
43
44
45
46
47
47
48
48
49
49
50
50
51
51
51
52
53
53
54
55
56
57
57
58
59
60
61
62
63
64
64
65
65
65
66
67
67
68
68
68
69
69
70
71
71
71
72
72
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4.3
4.4
June 2006
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VSC8558 Datasheet
Contents
4.5
4.6
4.4.5 GPIO Pin Configuration ..............................................................
4.4.6 100BASE-FX Control Register......................................................
CMODE..............................................................................................
4.5.1 CMODE Pins and Related Functions..............................................
4.5.2 Functions and Related CMODE Pins..............................................
4.5.3 CMODE Resistor Values ..............................................................
EEPROM ............................................................................................
4.6.1 EEPROM Contents Description .....................................................
4.6.2 Read/Write Access to the EEPROM ...............................................
72
73
73
74
74
76
77
77
79
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5
Electrical Specifications.......................................................... 81
5.1
DC Characteristics...............................................................................
5.1.1 VDDIO at 3.3 V.........................................................................
5.1.2 VDDIO at 2.5 V.........................................................................
5.1.3 VDDIO at 1.8 V.........................................................................
5.1.4 VDD at 3.3 V ............................................................................
5.1.5 MAC and SerDes Outputs ...........................................................
5.1.6 MAC and SerDes Inputs .............................................................
5.1.7 LED Pins ..................................................................................
5.1.8 JTAG Pins.................................................................................
Current Consumption ..........................................................................
AC Characteristics ...............................................................................
5.3.1 Reference Clock Input................................................................
5.3.2 Clock Output ............................................................................
5.3.3 JTAG Interface ..........................................................................
5.3.4 SMI Interface ...........................................................................
5.3.5 Device Reset ............................................................................
5.3.6 Serial LEDs ..............................................................................
Operating Conditions ...........................................................................
Stress Ratings ....................................................................................
81
81
82
82
83
83
84
84
85
85
86
86
87
87
88
89
90
91
91
5.2
5.3
5.4
5.5
6
Pin Descriptions ..................................................................... 92
6.1
6.2
Pin Diagram ....................................................................................... 92
Pin Identifications ............................................................................... 94
6.2.1 SerDes MAC Interface................................................................ 94
6.2.2 SerDes Media Interface.............................................................. 95
6.2.3 GPIO and SIGDET ..................................................................... 96
6.2.4 Twisted Pair Interface ................................................................ 96
6.2.5 Serial Management Interface ...................................................... 97
6.2.6 JTAG ....................................................................................... 98
6.2.7 Power Supply ........................................................................... 99
6.2.8 Miscellaneous ..........................................................................101
7
Package Information ............................................................ 103
7.1
7.2
7.3
Package Drawing ...............................................................................103
Thermal Specifications........................................................................105
Moisture Sensitivity ............................................................................105
June 2006
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