5800
AND
5801
BiMOS II
LATCHED DRIVERS
5800
AND
5801
BiMOS II LATCHED DRIVERS
The UCN5800A/L and UCN5801A/EP/LW latched-input BiMOS
ICs merge high-current, high-voltage outputs with CMOS logic. The
CMOS input section consists of 4 or 8 data (‘D’ type) latches with
associated common CLEAR, STROBE, and OUTPUT ENABLE
circuitry. The power outputs are bipolar npn Darlingtons. This merged
technology provides versatile, flexible interface. These BiMOS power
interface ICs greatly benefit the simplification of computer or micropro-
cessor I/O. The UCN5800A and UCN5800L each contain four latched
drivers; the UCN5801A, UCN5801EP, and UCN5801LW contain eight
latched drivers.
The UCN5800A/L and UCN5801A/EP/LW supersede the original
BiMOS latched-input driver ICs (UCN4400A and UCN4801A). These
second-generation devices are capable of much higher data input
rates and will typically operate at better than 5 MHz with a 5 V logic
supply. Circuit operation at 12 V affords substantial improvement over
the 5 MHz figure.
The CMOS inputs are compatible with standard CMOS and NMOS
circuits. TTL circuits may mandate the addition of input pull-up resis-
tors. The bipolar Darlington outputs are suitable for directly driving
many peripheral/power loads: relays, lamps, solenoids, small dc
motors, etc.
All devices have open-collector outputs and integral diodes for
inductive load transient suppression. The output transistors are
capable of sinking 500 mA and will withstand at least 50 V in the OFF
state. Because of limitations on package power dissipation, the simul-
taneous operation of all drivers at maximum rated current can only be
accomplished by a reduction in duty cycle. Outputs may be paralleled
for higher load current capability.
The UCN5800A is furnished in a standard 14-pin DIP; the
UCN5800L and UCN5801LW in surface-mountable SOICs; the
UCN5801A in a 22-pin DIP with 0.400" (10.16 mm) row centers; the
UCN5801EP in a 28-lead PLCC.
Data Sheet
26180.10B
UCN5800L
1
14
UCN5800A
CLEAR
STROBE
IN
1
IN
2
IN
3
IN
4
GROUND
1
2
3
4
5
6
7
14
V
DD
13
12
OUTPUT
ENABLE
SUPPLY
OUT
1
OUT
2
OUT
3
OUT
4
COMMON
LATCHES
11
10
9
8
Dwg. PP-014A
Note the UCN5800A (DIP) and the UCN5800L
(SOIC) are electrically identical and share a
common terminal number assignment.
ABSOLUTE MAXIMUM RATINGS
at
+25
°
C Free-Air Temperature
Output Voltage, V
CE
. . . . . . . . . . . . . . 50 V
Supply Voltage, V
DD
. . . . . . . . . . . . . . 15 V
Input Voltage Range,
V
IN
. . . . . . . . . . . -0.3 V to V
DD
+ 0.3 V
Continuous Collector Current,
l
C
. . . . . . . . . . . . . . . . . . . . . . 500 mA
Package Power Dissipation,
P
D
. . . . . . . . . . . . . . . . . . . . See Graph
Operating Temperature Range,
T
A
. . . . . . . . . . . . . . . . -20
°
C to +85
°
C
Storage Temperature Range,
T
S
. . . . . . . . . . . . . . . -55
°
C to +150
°
C
Caution: CMOS devices have input static
protection but are susceptible to damage when
exposed to extremely high static electrical
charges.
FEATURES
s
s
To 4.4 MHz Data Input Rate
s
s
High-Voltage,
s
High-Current Outputs
s
s
CMOS, NMOS,
TTL Compatible Inputs
Output Transient Protection
Internal Pull-Down Resistors
Low-Power CMOS Latches
Automotive Capable
Always order by complete part number, e.g.,
UCN5801EP
.
5800
AND
5801
BiMOS II
LATCHED DRIVERS
UCN5801A
CLEAR
STROBE
IN
1
IN
2
IN
3
IN
4
IN
5
IN
6
IN
7
IN
8
GROUND
1
2
3
4
5
6
7
8
9
10
11
22
V
DD
21
20
19
18
OUTPUT
ENABLE
SUPPLY
OUT
1
OUT
2
OUT
3
OUT
4
OUT
5
OUT
6
OUT
7
OUT
8
COMMON
OUTN
CLEAR
F
STROBE
A
OUTPUT
ENABLE
INN
D
E
E
C
B
C
B
A
C
B
G
G
Dwg. No. A-10,895A
LATCHES
17
16
15
14
13
12
TIMING CONDITIONS
(Logic Levels are V
DD
and Ground)
A.
Minimum Data Active Time Before Strobe Enabled
(Data Set-Up Time) ..........................................................
50 ns
B.
Minimum Data Active Time After Strobe Disabled
(Data Hold Time) ..............................................................
50 ns
C.
Minimum Strobe Pulse Width ..................................................125
ns
Dwg. PP-015
D.
Typical Time Between Strobe Activation and
Output On to Off Transition ............................................500
ns
E.
Minimum Time Between Strobe Activation and
Output Off to On Transition ............................................500
ns
UCN5801LW
CLEAR
STROBE
IN
1
IN
2
IN
3
IN
4
IN
5
IN
6
IN
7
IN
8
GROUND
NO
CONNECTION
1
2
3
4
5
6
7
8
9
10
11
12
NC
NC
V
DD
24
23
22
21
20
OUTPUT
ENABLE
SUPPLY
OUT
1
OUT
2
OUT
3
OUT
4
OUT
5
OUT
6
OUT
7
OUT
8
COMMON
NO
CONNECTION
Dwg. PP-015-1
F.
Minimum Clear Pulse Width ....................................................300
ns
G.
Minimum Data Pulse Width .....................................................225
ns
Information present at an input is transferred to its latch when the
STROBE is high. A high CLEAR input will set all latches to the output
OFF condition regardless of the data or STROBE input levels. A high
OUTPUT ENABLE will set all outputs to the OFF condition, regardless
of any other input conditions. When the OUTPUT ENABLE is low, the
outputs depend on the state of their respective latches.
LATCHES
19
18
17
16
15
14
13
TRUTH TABLE
OUTPUT
IN
N
0
1
X
X
X
X
STROBE
1
1
X
X
0
0
CLEAR
0
0
1
X
0
0
ENABLE
0
0
X
1
0
0
t-1
X
X
X
X
ON
OFF
OUT
N
t
OFF
ON
OFF
OFF
ON
OFF
X = irrelevant.
t-1 = previous output state.
t = present output state.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
PCB Design
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