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AD9229BCPZ-50

Description
IC 4-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, QCC48, LEAD FREE, MO-220-VKKD-2, LFCSP-48, Analog to Digital Converter
CategoryAnalog mixed-signal IC    converter   
File Size773KB,40 Pages
ManufacturerADI
Websitehttps://www.analog.com
Environmental Compliance  
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AD9229BCPZ-50 Overview

IC 4-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, QCC48, LEAD FREE, MO-220-VKKD-2, LFCSP-48, Analog to Digital Converter

AD9229BCPZ-50 Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerADI
Parts packaging codeQFN
package instructionLEAD FREE, MO-220-VKKD-2, LFCSP-48
Contacts48
Reach Compliance Codeunknown
ECCN codeEAR99
Converter typeADC, PROPRIETARY METHOD
JESD-30 codeS-XQCC-N48
JESD-609 codee3
length7 mm
Maximum linear error (EL)0.024%
Humidity sensitivity level3
Number of analog input channels4
Number of digits12
Number of functions1
Number of terminals48
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output bit codeOFFSET BINARY
Output formatSERIAL
Package body materialUNSPECIFIED
encapsulated codeHVQCCN
Encapsulate equivalent codeLCC48,.27SQ,20
Package shapeSQUARE
Package formCHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)240
power supply3 V
Certification statusNot Qualified
Sampling rate50 MHz
Sample and hold/Track and holdTRACK
Maximum seat height1 mm
Nominal supply voltage3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn)
Terminal formNO LEAD
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature40
width7 mm
Quad, 12-Bit, 50/65 MSPS,
Serial, LVDS, 3 V A/D Converter
AD9229
FEATURES
Four ADCs in 1 package
Serial LVDS digital output data rates
to 780 Mbps (ANSI-644)
Data and frame clock outputs
SNR = 69.5 dB (to Nyquist)
Excellent linearity
DNL = ±0.3 LSB (typical)
INL = ±0.4 LSB (typical)
400 MHz full power analog bandwidth
Power dissipation
1,350 mW at 65 MSPS
985 mW at 50 MSPS
1 V p-p to 2 V p-p input voltage range
3.0 V supply operation
Power-down mode
Digital test pattern enable for timing alignments
FUNCTIONAL BLOCK DIAGRAM
PDWN
DTP
DRVDD
DRGND
AD9229
VIN+A
VIN–A
VIN+B
VIN–B
VIN+C
VIN–C
VIN+D
VIN–D
SHA
SHA
SHA
SHA
PIPELINE
ADC
12
SERIAL
LVDS
D+A
D–A
D+B
D–B
D+C
D–C
D+D
D–D
PIPELINE
ADC
12
SERIAL
LVDS
PIPELINE
ADC
12
SERIAL
LVDS
PIPELINE
ADC
12
SERIAL
LVDS
VREF
SENSE
0.5V
REFT
REFB
REF
SELECT
DATA RATE
MULTIPLIER
FCO+
FCO–
DCO+
DCO–
04418-001
APPLICATIONS
Digital beam-forming systems for ultrasound
Wireless and wired broadband communications
Communication test equipment
AGND
LVDSBIAS
CLK
Figure 1.
GENERAL DESCRIPTION
The AD9229 is a quad, 12-bit, 65 MSPS analog-to-digital
converter (ADC) with an on-chip sample-and-hold circuit that
is designed for low cost, low power, small size, and ease of use.
The product operates at up to a 65 MSPS conversion rate and is
optimized for outstanding dynamic performance in applications
where a small package size is critical.
The ADC requires a single 3 V power supply and TTL-/CMOS-
compatible sample rate clock for full performance operation.
No external reference or driver components are required for
many applications.
The ADC automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. A data clock (DCO) for
capturing data on the output and a frame clock (FCO) trigger
for signaling a new output byte are provided. Power-down is
supported and typically consumes 3 mW when enabled.
Fabricated with an advanced CMOS process, the AD9229 is
available in a Pb-free, 48-lead LFCSP package. It is specified
over the industrial temperature range of –40°C to +85°C.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
Four ADCs are contained in a small, space-saving package.
A data clock out (DCO) is provided, which operates up to
390 MHz and supports double-data rate operation (DDR).
The outputs of each ADC are serialized LVDS with data
rates up to 780 Mbps (12 bits × 65 MSPS).
The AD9229 operates from a single 3.0 V power supply.
Packaged in a Pb-free, 48-lead LFCSP package.
The internal clock duty cycle stabilizer maintains
performance over a wide range of input clock duty cycles.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.

AD9229BCPZ-50 Related Products

AD9229BCPZ-50 AD9229BCPZRL7-50
Description IC 4-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, QCC48, LEAD FREE, MO-220-VKKD-2, LFCSP-48, Analog to Digital Converter IC 4-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, QCC48, LEAD FREE, MO-220-VKKD-2, LFCSP-48, Analog to Digital Converter
Is it lead-free? Lead free Lead free
Is it Rohs certified? conform to conform to
Maker ADI ADI
Parts packaging code QFN QFN
package instruction LEAD FREE, MO-220-VKKD-2, LFCSP-48 LEAD FREE, MO-220-VKKD-2, LFCSP-48
Contacts 48 48
Reach Compliance Code unknown unknown
ECCN code EAR99 EAR99
Converter type ADC, PROPRIETARY METHOD ADC, PROPRIETARY METHOD
JESD-30 code S-XQCC-N48 S-XQCC-N48
JESD-609 code e3 e3
length 7 mm 7 mm
Maximum linear error (EL) 0.024% 0.024%
Humidity sensitivity level 3 3
Number of analog input channels 4 4
Number of digits 12 12
Number of functions 1 1
Number of terminals 48 48
Maximum operating temperature 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C
Output bit code OFFSET BINARY OFFSET BINARY
Output format SERIAL SERIAL
Package body material UNSPECIFIED UNSPECIFIED
encapsulated code HVQCCN HVQCCN
Encapsulate equivalent code LCC48,.27SQ,20 LCC48,.27SQ,20
Package shape SQUARE SQUARE
Package form CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius) 240 260
power supply 3 V 3 V
Certification status Not Qualified Not Qualified
Sampling rate 50 MHz 50 MHz
Sample and hold/Track and hold TRACK TRACK
Maximum seat height 1 mm 1 mm
Nominal supply voltage 3 V 3 V
surface mount YES YES
technology CMOS CMOS
Temperature level INDUSTRIAL INDUSTRIAL
Terminal surface Matte Tin (Sn) Matte Tin (Sn)
Terminal form NO LEAD NO LEAD
Terminal pitch 0.5 mm 0.5 mm
Terminal location QUAD QUAD
Maximum time at peak reflow temperature 40 40
width 7 mm 7 mm
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