ADF4112BRU-REEL7 datasheet, PDF

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ADF4112BRU-REEL7: DescriptionSingle, Integer-N 3.0 GHz PLL With Programmable Prescaler And Charge Pump; CategoryAnalog mixed-signal IC The signal circuit; File Size458KB，28 Pages; ManufacturerADI; Websitehttps://www.analog.com

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Single, Integer-N 3.0 GHz PLL With Programmable Prescaler And Charge Pump

ADF4112BRU-REEL7 Parametric

Parameter Name	Attribute value
Source Url Status Check Date	2013-05-01 14:56:35.577
Brand Name	Analog Devices Inc
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	ADI
Parts packaging code	TSSOP
package instruction	MO-153AB, TSSOP-16
Contacts	16
Manufacturer packaging code	RU-16
Reach Compliance Code	not_compliant
ECCN code	5A991.B
Other features	6-BIT SWALLOW COUNTER
Analog Integrated Circuits - Other Types	PLL FREQUENCY SYNTHESIZER
JESD-30 code	R-PDSO-G16
JESD-609 code	e0
length	5 mm
Humidity sensitivity level	1
Number of functions	1
Number of terminals	16
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP16,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	240
power supply	3/5 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply current (Isup)	4 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	BICMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	4.4 mm

ADF4112BRU-REEL7 Preview

Data Sheet

FEATURES

RF PLL Frequency Synthesizers

ADF4110/ADF4111/ADF4112/ADF4113

GENERAL DESCRIPTION

The ADF4110 family of frequency synthesizers can be used to

implement local oscillators in the upconversion and downcon-

version sections of wireless receivers and transmitters. They

consist of a low noise digital PFD (phase frequency detector), a

precision charge pump, a programmable reference divider,

programmable A and B counters, and a dual-modulus prescaler

(P/P + 1). The A (6-bit) and B (13-bit) counters, in conjunction

with the dual-modulus prescaler (P/P + 1), implement an N

divider (N = BP + A). In addition, the 14-bit reference counter

(R counter) allows selectable REFIN frequencies at the PFD

input. A complete phase-locked loop (PLL) can be implemented

if the synthesizer is used with an external loop filter and voltage

controlled oscillator (VCO).

Control of all the on-chip registers is via a simple 3-wire

interface. The devices operate with a power supply ranging

from 2.7 V to 5.5 V and can be powered down when not in use.

ADF4110: 550 MHz; ADF4111: 1.2 GHz; ADF4112: 3.0 GHz;

ADF4113: 4.0 GHz

2.7 V to 5.5 V power supply

Separate charge pump supply (V

) allows extended tuning

voltage in 3 V systems

Programmable dual-modulus prescaler 8/9, 16/17, 32/33,

64/65

Programmable charge pump currents

Programmable antibacklash pulse width

3-wire serial interface

Analog and digital lock detect

Hardware and software power-down mode

APPLICATIONS

Base stations for wireless radio (GSM, PCS, DCS, CDMA,

WCDMA)

Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA)

Wireless LANS

Communications test equipment

CATV equipment

FUNCTIONAL BLOCK DIAGRAM

CPGND

REFERENCE

SET

REF

14-BIT

R COUNTER

LATCH

PHASE

FREQUENCY

DETECTOR

CHARGE

PUMP

CLK

DATA

24-BIT

INPUT REGISTER

FUNCTION

LATCH

A, B COUNTER

LATCH

LOCK

DETECT

CURRENT

SETTING 1

CURRENT

SETTING 2

OUT

CPI3 CPI2 CPI1 CPI6 CPI5 CPI4

FROM

FUNCTION

LATCH

N = BP + A

13-BIT

B COUNTER

LOAD

6-BIT

A COUNTER

HIGH Z

MUX

MUXOUT

OUT

PRESCALER

P/P +1

M2 M1

AGND

DGND

Figure 1. Functional Block Diagram

Rev. F

Document Feedback

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

03496-0-001

ADF4110/ADF4111

ADF4112/ADF4113

ADF4110/ADF4111/ADF4112/ADF4113

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Characteristics ..................................................................... 5

Absolute Maximum Ratings ............................................................ 6

Transistor Count ........................................................................... 6

ESD Caution .................................................................................. 6

Pin Configurations and Function Descriptions ........................... 7

Typical Performance Characteristics ............................................. 8

Circuit Description ......................................................................... 12

Reference Input Section ............................................................. 12

RF Input Stage ............................................................................. 12

Prescaler (P/P + 1) ...................................................................... 12

A and B Counters ....................................................................... 12

R Counter .................................................................................... 12

Data Sheet

Phase Frequency Detector (PFD) and Charge Pump............ 13

Muxout and Lock Detect ........................................................... 13

Input Shift Register .................................................................... 13

Function Latch ............................................................................ 19

Initialization Latch ..................................................................... 20

Device Programming after Initial Power-Up ......................... 20

Resynchronizing the Prescaler Output .................................... 21

Applications..................................................................................... 22

Local Oscillator for GSM Base Station Transmitter .............. 22

Using a D/A Converter to Drive the R

SET

Pin ......................... 23

Shutdown Circuit ....................................................................... 23

Wideband PLL ............................................................................ 23

Direct Conversion Modulator .................................................. 25

Interfacing ................................................................................... 26

PCB Design Guidelines for Chip Scale Package .................... 26

Outline Dimensions ....................................................................... 27

Ordering Guide ............................................................................... 28

REVISION HISTORY

1/13—Rev. E to Rev. F

Changes to Table 1 ............................................................................. 4

Changes to Ordering Guide ...........................................................28

8/12—Rev. D to Rev. E

Changed CP-20-1 to CP-20-6 ........................................... Universal

Updated Outline Dimensions ........................................................28

Changes to Ordering Guide ...........................................................28

5/12—Rev. C to Rev. D

Changes to Figure 2 ........................................................................... 5

Changes to Figure 4 and Table 4 ...................................................... 7

Updated Outline Dimensions ........................................................28

Changes to Ordering Guide ...........................................................28

3/04—Data sheet changed from Rev. B to Rev. C.

Updated Format .................................................................. Universal

Changes to Specifications ................................................................. 2

Changes to Figure 32 .......................................................................22

Changes to the Ordering Guide.....................................................28

3/03—Data sheet changed from Rev. A to Rev. B.

Edits to Specifications ....................................................................... 2

Updated OUTLINE DIMENSIONS ............................................. 24

1/01—Data sheet changed from Rev. 0 to Rev. A.

Changes to DC Specifications in B Version, B Chips,

Unit, and Test Conditions/Comments Columns ..................... 2

Changes to Absolute Maximum Rating ......................................... 4

Changes to FR

A Function Test ..................................................... 5

Changes to Figure 8 ........................................................................... 7

New Graph Added—TPC 22 ........................................................... 9

Change to PD Polarity Box in Table V ......................................... 15

Change to PD Polarity Box in Table VI ........................................ 16

Change to PD Polarity Paragraph ................................................. 17

Addition of New Material

(PCB Design Guidelines for Chip–Scale package) ................ 23

Replacement of CP-20 Outline with CP-20 [2] Outline ............ 24

Rev. F | Page 2 of 28

Data Sheet

SPECIFICATIONS

ADF4110/ADF4111/ADF4112/ADF4113

= DV

= 3 V ± 10%, 5 V ± 10%; AV

≤V

≤ 6.0 V; AGND = DGND = CPGND = 0 V; R

SET

= 4.7 kΩ; dBm referred to 50 Ω;

= T

MIN

to T

MAX

, unless otherwise noted. Operating temperature range is as follows: B Version: −40°C to +85°C.

Table 1.

Parameter

RF CHARACTERISTICS (3 V)

RF Input Sensitivity

RF Input Frequency

ADF4110

ADF4111

ADF4112

ADF4113

Maximum Allowable Prescaler Output

Frequency

RF CHARACTERISTICS (5 V)

RF Input Sensitivity

RF Input Frequency

ADF4110

ADF4111

ADF4112

ADF4113

Maximum Allowable Prescaler Output

Frequency

REFIN CHARACTERISTICS

REFIN Input Frequency

Reference Input Sensitivity

REFIN Input Capacitance

REFIN Input Current

PHASE DETECTOR FREQUENCY

CHARGE PUMP

Sink/Source

High Value

Low Value

Absolute Accuracy

SET

Range

3-State Leakage Current

Sink and Source Current Matching

vs. V

vs. Temperature

LOGIC INPUTS

INH

, Input High Voltage

INL

, Input Low Voltage

INH

INL

, Input Current

, Input Capacitance

LOGIC OUTPUTS

, Output High Voltage

, Output Low Voltage

B Version

−15/0

80/550

50/550

0.08/1.2

0.2/3.0

0.1/3.0

0.2/3.7

165

−10/0

80/550

0.08/1.4

0.1/3.0

0.2/3.7

0.2/4.0

200

5/104

0.4/AV

3.0/AV

±100

B Chips

−15/0

80/550

50/550

0.08/1.2

0.2/3.0

0.1/3.0

0.2/3.7

165

−10/0

80/550

0.08/1.4

0.1/3.0

0.2/3.7

0.2/4.0

200

5/104

0.4/AV

3.0/AV

±100

Unit

dBm min/max

MHz min/max

GHz min/max

MHz max

dBm min/max

MHz min/max

GHz min/max

MHz max

MHz min/max

V p-p min/max

pF max

µA max

MHz max

For f < 5 MHz, ensure SR > 100 V/µs.

= 3.3 V, biased at AV

/2. See Note 3.

= 5 V, biased at AV

/2. See Note

For lower frequencies, ensure SR > 50 V/µs.

For lower frequencies, ensure SR > 75 V/µs.

For lower frequencies, ensure SR > 130 V/µs.

Input level = −5 dBm.

For lower frequencies, ensure slew rate

(SR) > 30 V/µs.

Input level = −10 dBm.

For lower frequencies, ensure SR > 30 V/µs.

For lower frequencies, ensure SR > 75 V/µs.

Input level = −10 dBm.

Input level = −10 dBm. For lower frequencies,

ensure SR > 130 V/µs.

Test Conditions/Comments

See

Figure 29

for input circuit.

625

2.5

2.7/10

1.5

0.8 × DV

0.2 × DV

±1

– 0.4

0.4

625

2.5

2.7/10

1.5

0.8 × DV

0.2 × DV

±1

– 0.4

0.4

mA typ

µA typ

% typ

kΩ typ

nA typ

% typ

V min

V max

µA max

pF max

V min

V max

Programmable (see

Table 9

With R

SET

= 4.7 kΩ.

With R

SET

= 4.7 kΩ.

See

Table 9

0.5 V ≤ V

≤ V

– 0.5 V.

0.5 V ≤ V

≤ V

– 0.5 V.

= V

/2.

= 500 µA.

Rev. F | Page 3 of 28

ADF4110/ADF4111/ADF4112/ADF4113

Parameter

POWER SUPPLIES

DD 5

(AI

+ DI

)

ADF4110

ADF4111

ADF4112

ADF4113

Low Power Sleep Mode

NOISE CHARACTERISTICS

ADF4113 Normalized Phase Noise Floor

Phase Noise Performance

ADF4110: 540 MHz Output

ADF4111: 900 MHz Output

ADF4112: 900 MHz Output

ADF4113: 900 MHz Output

ADF4111: 836 MHz Output

ADF4112: 1750 MHz Output

ADF4112: 1960 MHz Output

ADF4113: 1960 MHz Output

ADF4113: 3100 MHz Output

Spurious Signals

ADF4110: 540 MHz Output

ADF4111: 900 MHz Output

ADF4112: 900 MHz Output

ADF4113: 900 MHz Output

ADF4111: 836 MHz Output

ADF4112: 1750 MHz Output

ADF4112: 1960 MHz Output

ADF4113: 1960 MHz Output

ADF4113: 3100 MHz Output

Data Sheet

Unit

V min/V max

mA max

µA typ

dBc/Hz typ

dBc typ

@ VCO output.

@ 1 kHz offset and 200 kHz PFD frequency.

@ 300 Hz offset and 30 kHz PFD frequency.

@ 1 kHz offset and 200 kHz PFD frequency.

@ 200 Hz offset and 10 kHz PFD frequency.

@ 1 kHz offset and 200 kHz PFD frequency.

@ 1 kHz offset and 1 MHz PFD frequency.

@ 200 kHz/400 kHz and 200 kHz PFD frequency.

@ 30 kHz/60 kHz and 30 kHz PFD frequency.

@ 200 kHz/400 kHz and 200 kHz PFD frequency.

@ 10 kHz/20 kHz and 10 kHz PFD frequency.

@ 200 kHz/400 kHz and 200 kHz PFD frequency.

@ 1 MHz/2 MHz and 1 MHz PFD frequency.

≤ V

≤ 6.0 V. See

Figure 25

and

Figure 26

4.5 mA typical.

6.5 mA typical.

8.5 mA typical.

= 25°C.

Test Conditions/Comments

B Version

2.7/5.5

/6.0

5.5

7.5

0.5

−215

−91

−87

−90

−91

−78

−86

−66

−84

−85

−86

−97/−106

−98/−110

−91/−100

−100/−110

−81/−84

−88/−90

−65/−73

−80/−84

−80/−82

B Chips

2.7/5.5

/6.0

4.5

6.5

8.5

0.5

−215

−91

−87

−90

−91

−78

−86

−66

−84

−85

−86

−97/−106

−98/−110

−91/−100

−100/−110

−81/−84

−88/−90

−65/−73

−80/−84

−82/−82

The B chip specifications are given as typical values.

This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that

is less than this value.

AC coupling ensures AV

/2 bias. See Figure 33 for a typical circuit.

Guaranteed by design.

= 25°C; AV

= DV

= 3 V; P = 16; SYNC = 0; DLY = 0; RF

for ADF4110 = 540 MHz; RF

for ADF4111, ADF4112, ADF4113 = 900 MHz.

The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO, PN

TOT

, and subtracting 20logN (where N is the N divider

value) and 10logF

PFD

: PN

SYNTH

= PN

TOT

– 10logF

PFD

– 20logN.

The phase noise is measured with the EV-ADF411XSD1Z evaluation board and the HP8562E spectrum analyzer. The spectrum analyzer provides the REFIN for the

synthesizer (f

REFOUT

= 10 MHz @ 0 dBm). SYNC = 0; DLY = 0 (Table 7).

REFIN

= 10 MHz; f

PFD

= 200 kHz; offset frequency = 1 kHz; f

= 540 MHz; N = 2700; loop B/W = 20 kHz.

REFIN

= 10 MHz; f

PFD

= 200 kHz; offset frequency = 1 kHz; f

= 900 MHz; N = 4500; loop B/W = 20 kHz.

REFIN

= 10 MHz; f

PFD

= 30 kHz; offset frequency = 300 Hz; f

= 836 MHz; N = 27867; loop B/W = 3 kHz.

REFIN

= 10 MHz; f

PFD

= 200 kHz; offset frequency = 1 kHz; f

= 1750 MHz; N = 8750; loop B/W = 20 kHz

REFIN

= 10 MHz; f

PFD

= 10 kHz; offset frequency = 200 Hz; f

= 1750 MHz; N = 175000; loop B/W = 1 kHz.

REFIN

= 10 MHz; f

PFD

= 200 kHz; offset frequency = 1 kHz; f

= 1960 MHz; N = 9800; loop B/W = 20 kHz.

REFIN

= 10 MHz; f

PFD

= 1 MHz; offset frequency = 1 kHz; f

= 3100 MHz; N = 3100; loop B/W = 20 kHz.

Rev. F | Page 4 of 28

Data Sheet

TIMING CHARACTERISTICS

ADF4110/ADF4111/ADF4112/ADF4113

Guaranteed by design but not production tested. AV

= DV

= 3 V ± 10%, 5 V ± 10%; AV

≤ V

≤ 6 V;

AGND = DGND = CPGND = 0 V; R

SET

= 4.7 kΩ; T

= T

MIN

to T

MAX

, unless otherwise noted.

Table 2.

Parameter

Limit at T

MIN

to T

MAX

(B Version)

Unit

ns min

Test Conditions/Comments

DATA to CLOCK setup time

DATA to CLOCK hold time

CLOCK high duration

CLOCK low duration

CLOCK to LE setup time

LE pulse width

CLOCK

DATA

DB23 (MSB)

DB22

DB2

DB1

(CONTROL BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

03496-002

Figure 2. Timing Diagram

Rev. F | Page 5 of 28

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Brand Name	Analog Devices Inc	Analog Devices Inc	Analog Devices Inc	Analog Devices Inc	Analog Devices Inc	Analog Devices Inc
Is it lead-free?	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead
Is it Rohs certified?	incompatible	conform to	conform to	incompatible	incompatible	incompatible
Maker	ADI	ADI	ADI	ADI	ADI	ADI
Parts packaging code	TSSOP	QFN	QFN	TSSOP	TSSOP	TSSOP
package instruction	MO-153AB, TSSOP-16	VQCCN, LCC20,.16SQ,20	VQCCN, LCC20,.16SQ,20	TSSOP, TSSOP16,.25	TSSOP, TSSOP16,.25	TSSOP, TSSOP16,.25
Contacts	16	20	20	16	16	16
Manufacturer packaging code	RU-16	CP-20-6	CP-20-6	RU-16	RU-16	RU-16
Reach Compliance Code	not_compliant	compliant	compliant	not_compliant	not_compliant	not_compliant
Other features	6-BIT SWALLOW COUNTER	6-BIT SWALLOW COUNTER	6-BIT SWALLOW COUNTER	6-BIT SWALLOW COUNTER	6-BIT SWALLOW COUNTER	6-BIT SWALLOW COUNTER
Analog Integrated Circuits - Other Types	PLL FREQUENCY SYNTHESIZER	PLL FREQUENCY SYNTHESIZER	PLL FREQUENCY SYNTHESIZER	PLL FREQUENCY SYNTHESIZER	PLL FREQUENCY SYNTHESIZER	PLL FREQUENCY SYNTHESIZER
JESD-30 code	R-PDSO-G16	S-CQCC-N20	S-CQCC-N20	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16
JESD-609 code	e0	e3	e3	e0	e0	e0
length	5 mm	4 mm	4 mm	5 mm	5 mm	5 mm
Humidity sensitivity level	1	3	3	1	1	1
Number of functions	1	1	1	1	1	1
Number of terminals	16	20	20	16	16	16
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	VQCCN	VQCCN	TSSOP	TSSOP	TSSOP
Encapsulate equivalent code	TSSOP16,.25	LCC20,.16SQ,20	LCC20,.16SQ,20	TSSOP16,.25	TSSOP16,.25	TSSOP16,.25
Package shape	RECTANGULAR	SQUARE	SQUARE	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	CHIP CARRIER, VERY THIN PROFILE	CHIP CARRIER, VERY THIN PROFILE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	240	260	260	240	240	240
power supply	3/5 V	3/5 V	3/5 V	3/5 V	3/5 V	3/5 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	1 mm	1 mm	1.2 mm	1.2 mm	1.2 mm
Maximum supply current (Isup)	4 mA	11 mA	5.5 mA	1.7 mA	11 mA	11 mA
Maximum supply voltage (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage (Vsup)	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V
Nominal supply voltage (Vsup)	3 V	3 V	3 V	3 V	3 V	3 V
surface mount	YES	YES	YES	YES	YES	YES
technology	BICMOS	BICMOS	BICMOS	BICMOS	BICMOS	BICMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	Tin/Lead (Sn85Pb15)	Matte Tin (Sn)	Matte Tin (Sn)	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING	NO LEAD	NO LEAD	GULL WING	GULL WING	GULL WING
Terminal pitch	0.65 mm	0.5 mm	0.5 mm	0.65 mm	0.65 mm	0.65 mm
Terminal location	DUAL	QUAD	QUAD	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	30	NOT SPECIFIED	40	30	30	30
width	4.4 mm	4 mm	4 mm	4.4 mm	4.4 mm	4.4 mm
Source Url Status Check Date	2013-05-01 14:56:35.577	-	-	2013-05-01 14:56:35.545	2013-05-01 14:56:35.589	2013-05-01 14:56:35.59
ECCN code	5A991.B	5A991.B	5A991.B	5A991.B	5A991.B	-

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