Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio
CODEC with DSP features
FEATURES
General
•
Low power consumption
•
3.0 V power supply
•
256, 384 and 512f
s
system clock
•
Small package size (SSOP28)
•
ADC plus integrated high pass filter to cancel DC offset
•
Overload detector for easy record level control
•
Separate power control for ADC and DAC
•
Integrated digital filter plus DAC
•
No analog post filter required for DAC
•
Easy application
•
Functions controllable by microcontroller interface.
Multiple format input interface
•
I
2
S-bus, MSB-justified and LSB-justified format
compatible
•
1f
s
input and output format data rate.
DAC digital sound processing
•
Digital volume control
•
Digital tone control, bass boost and treble
•
dB-linear volume and tone control (low microcontroller
load)
•
Digital de-emphasis for 32, 44.1 and 48 kHz f
s
•
Soft mute.
Advanced audio configuration
•
Stereo single-ended input configuration
•
Stereo line output (under microcontroller volume
control)
•
Power-down click prevention circuitry
•
High linearity, dynamic range, low distortion.
ORDERING INFORMATION
TYPE
NUMBER
UDA1340M
PACKAGE
NAME
SSOP28
DESCRIPTION
plastic shrink small outline package; 28 leads; body width 5.3 mm
GENERAL DESCRIPTION
UDA1340
The UDA1340 is a single-chip stereo Analog-to-Digital
Converter (ADC) and Digital-to-Analog Converter (DAC)
with signal processing features employing bitstream
conversion techniques. The low power consumption and
low voltage requirements make the device eminently
suitable for use in low-voltage low-power portable digital
audio equipment which incorporates recording and
playback functions.
The UDA1340 supports the I
2
S-bus data format with word
lengths of up to 20 bits, the MSB-justified data format with
word lengths of up to 20 bits and the LSB justified serial
data format with word lengths of 16, 18 and 20 bits.
The UDA1340 has special sound processing features in
playback mode, de-emphasis, volume, bass boost, treble,
and soft mute, which can be controlled via the
microcontroller interface.
VERSION
SOT341-1
1997 Jul 09
2
Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio
CODEC with DSP features
QUICK REFERENCE DATA
SYMBOL
Supply
V
DDA(ADC)
V
DDA(DAC)
V
DDO
V
DDD
I
DDA(ADC)
I
DDA(DAC)
I
DDO
I
DDD
I
PD(ADC)
I
PD(DAC)
T
amb
V
I(rms)
(THD + N)/S
S/N
α
cs
V
o(rms)
(THD + N)/S
S/N
α
cs
P
ADDA
P
DA
P
AD
P
PD
ADC analog supply voltage
DAC analog supply voltage
operational amplifiers supply voltage
digital supply voltage
ADC supply current
DAC supply current
operational amplifier supply current
digital supply current
digital ADC power-down supply current
digital DAC power-down supply current
operating ambient temperature
2.7
2.7
2.7
2.7
−
−
−
−
−
−
−20
−
at 0 dB
at
−60
dB; A-weighted
V
i
= 0 V; A-weighted
−
−
−
−
−
at 0 dB
at
−60
dB; A-weighted
code = 0; A weighted
−
−
−
−
−
−
−
−
3.0
3.0
3.0
3.0
4.5
3.5
4
6
3
3
−
PARAMETER
CONDITIONS
MIN.
TYP.
UDA1340
MAX.
UNIT
3.6
3.6
3.6
3.6
−
−
−
−
−
−
+85
−
−80
−30
−
−
−
−80
−
−
−
−
−
−
−
V
V
V
V
mA
mA
mA
mA
mA
mA
°
C
Analog-to-digital converter
input voltage (RMS value)
total harmonic distortion plus
noise-to-signal ratio
signal-to-noise ratio
channel separation
0.8
−85
−35
95
100
V
dB
dBA
dBA
dB
Digital-to-analog converter
output voltage (RMS value)
total harmonic distortion plus
noise-to-signal ratio
signal-to-noise ratio
channel separation
0.8
−85
−35
100
100
V
dB
dBA
dBA
dB
Power performance
power consumption in record and
playback mode
power consumption in playback only
mode
power consumption in record only
mode
power consumption in power-down
mode
54
33
27
6
mW
mW
mW
mW
1997 Jul 09
3
Philips Semiconductors
Preliminary specification
Low-voltage low-power stereo audio
CODEC with DSP features
PINNING
SYMBOL
V
SSA(ADC)
V
DDA(ADC)
VINL
V
ref(A)
VINR
V
ADCN
V
ADCP
TEST1
OVERFL
V
DDD
V
SSD
SYSCLK
L3MODE
L3CLOCK
L3DATA
BCK
WS
DATAO
DATAI
TEST3
TEST2
V
SSA(DAC)
V
DDA(DAC)
VOUTR
V
DDO
VOUTL
V
SSO
V
ref(D)
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Description
ADC analog ground
ADC analog supply voltage
ADC input left
ADC reference voltage
ADC input right
ADC negative reference voltage
ADC positive reference voltage
test control 1 (pull-down)
overload flag output
digital supply voltage
digital ground
system clock 256, 384 or 512f
s
L3-bus mode input
L3-bus clock input
L3-bus data input
bit clock input
word selection input
data output
data input
test output
test control 2 (pull-down)
DAC analog ground
DAC analog supply voltage
DAC output right
operational amplifier supply voltage
DAC output left
operational amplifier ground
DAC reference voltage
MGG838
UDA1340
handbook, halfpage
VSSA(ADC) 1
VDDA(ADC) 2
VINL 3
Vref(A) 4
VINR 5
VADCN 6
VADCP 7
TEST1 8
OVERFL 9
VDDD 10
VSSD 11
SYSCLK 12
L3MODE 13
L3CLOCK 14
28 Vref(D)
27 VSSO
26 VOUTL
25 VDDO
24 VOUTR
23 VDDA(DAC)
UDA1340
22 VSSA(DAC)
21 TEST2
20 TEST3
19 DATAI
18 DATAO
17 WS
16 BCK
15 L3DATA
Fig.2 Pin configuration.
1997 Jul 09
5
Real-time operating system RTOS
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